Most standard numbering seems to be upper left is pin 1 and go counter-clockwise.

Photograph in package

Obviously if you have the pinout or, second best, the PCB, you should just be careful and try to line it up with the package. Sometimes though this will be impractical or too late.

Power rails

PMOS is slower and thus requires a larger area to match speed to NMOS. Example standard cell active area:

Notice that the left side is smaller than the right? This means that the left side is NMOS and the right side is PMOS. Since NMOS on the left likes to connect to ground (V-) and PMOS on the right likes to connect to power (V+) we have identified the power nets. This can then be traced as needed.

If the cells are matched size or its a specialized chip you might not have this luxury. In that case start looking for connections to ground rings. For example, in this chip power pins are very distinctive because the protection network is very different, it feeds directly to the power ring around the chip, and the input is a lot larger:

Functional grouping

More often than not you can figure out a lot of pins based on their clustering and general layout. For example, if you know you have a 16 bit bus look for 16 similar pins. The routing should be very regular and distinctive since most pins won't be both inputs and outputs.

determining_pinout.txt · Last modified: 2013/10/20 10:59 (external edit)
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