- Sample prep
See also: captured chips
Note: ROM specific tools are covered on a separate page
The general consensus is that planarized chips can be semi-automatically reverse engineered using high contrast images (confocal and/or SEM). However, no-one in the open community has produced a tool that accelerates capturing non-planarized chips. Although metal has proven difficult, I suspect that it would be relatively easy to make a tool to capture the active area of a delayered IC.
Proprietary internal tool. Some screenshots have been released
As of 2016, I've heard rumors that its analysis capabilities are not very good and its mostly a glorified image viewer with some doodling capabilities. Since I've never used the tool I can't really say
Above: some pictures from http://www.iacr.org/archive/ches2009/57470361/57470361.pdf
The highest profile FOSS tool. Tutorials and other stuff available.
Users have noted significant stability issues. I (JM) tried tool again in 2016 and noted considerable stability improvements, but still had it crash on me before I was able to get any results. Still, it might not take that much work to stabilize the tool and unite the community behind it.
Known to primarily use photoshop. Focus is on tracing specific (security) circuits rather than trying to capture an entire design
An experimental semi-automated polygon capture tool for chips using lambda rules (grid layout)
TODO: add links to github project
Internal python tool to help draw polygons. Not publicly released
They also explored automation