United Microelectronic Corporation (UMC)
Mostly copper with thick aluminum on the top layer.
1.8V core with I/O up to 3.3V. Many mixed-signal devices will have an on-die LDO for generating 1.8 from 3.3 however higher end devices such as programmable logic typically expect an external 1.8V supply.
4-5 aluminum layers with tungsten vias, titanium-based barrier metal, and cobalt silicide contacts.
Partial design rules and FIB sections at http://siliconexposed.blogspot.com/2014/02/process-overview-umc-180nm-envm.html
Power ring and pad layouts can vary somewhat, as does presence or absence of CMP filler between bond pads.
On-die Flash/EEPROM option available.
The CMP filler pattern is distinctive and can be used as positive ID. Fill polygons are rectangles with 2:1 aspect ratio, long side oriented parallel to the prevailing routing direction.
CMP fill pattern table (measured from XC2C32A)
|Layer||Width||Height||X pitch (μm)||Y pitch (μm)||Conditions|
|M3||3000||825||3870||1960||With overglass removed, M4 present|
|M3||3075||1125||3952||1995||With M3 removed|