Lists of devices
Xilinx CoolRunner-II CPLD with 32 macrocells. The -A version supports two I/O banks while the baseline XC2C32 only has one.
180nm 4-metal process.
CPG56 - 0.5mm chip-scale BGA.
[Xilinx logo] 2C32A
Die size: 1895 x 1710 μm (3.24 mm^2)
Junction between VCCIO1 (left) and VCCIO2 (right) at bottom center of die. Note vias from ground ring to ground pad at bottom.
Top metal (NS50xU)
Active area Dash etch (MIT100x)
Various intermediate laps, browse around