Because of the way contacts and cell interconnec

Two more or less parallel wires circle the chip. Every power rail is hand routed where it needs to go and the rails are interleaved so that they don't need to cross. Most common with 2M chips. Example power routing on ST 24C02:

Perimeter has one metal layer with a large VDD bus and a second with a large VSS bus. They sandwich on top of each other to provide some filtering capacitance. Common on modern CMP chips (90s maybe?).

Obviously only on many metal chips (6+) as this requires significant resources. However, it does make the routing much easier and allows very clean power distribution.