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Photograph in package

Obviously if you have the pinout or, second best, the PCB, you should just be careful and try to line it up with the package. Sometimes though this will be impractical or too late.

Power rails

PMOS is slower and thus requires a larger area to match speed to NMOS. Example standard cell active area:

Notice that the right side is larger? This means that the right side is PMOS and the left side is NMOS. Since NMOS likes to connect to ground and PMOS likes to connect to V+ the right side is V+ and the left side is V-.

Functional grouping

More often than not you can figure out a lot of pins based on their clustering and general layout. For example, if you know you have a 16 bit bus look for 16 similar pins. The routing should be very regular and distinctive since most pins won't be both inputs and outputs.

 
determining_pinout.1330672493.txt.gz · Last modified: 2013/10/20 14:59 (external edit)
 
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