This is an old revision of the document!
Table of Contents
Xilinx CoolRunner-II CPLD with 32 macrocells. The -A version supports two I/O banks while the baseline XC2C32 only has one.
180nm 4-metal process.
Package
CPG56 - 0.5mm chip-scale BGA.
Markings:
[Xilinx logo] 2C32A F40731-1049 PHILIPPINES C4-AMS 6C
Die overview (metal 4)
Die size: 1895 x 1710 μm (3.24 mm^2)
Floorplan (metal 4)
Plan view closeups (metal 4)
Die logo
Output bus from function block 2 macrocells to I/O bank 1
Copyright notice (upside-down in bottom left corner)
VCCIO junction
Junction between VCCIO1 (left) and VCCIO2 (right) at bottom center of die. Note vias from ground ring to ground pad at bottom.
ZIA wiring
Maps
Cross sections
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
