10/100mbit SPI/parallel Ethernet controller.

Package

44-pin QFN, decapped live.

Die

Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.

Map

Close-up of dense logic area at upper right:

Partial HF delayer of SRAM. Confirmed to be same process as PIC32 based on SRAM cell pitch.

 
azonenberg/microchip/enc424j600.txt · Last modified: 2015/01/04 17:50 (external edit)
 
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