Differences

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--- carrier:th [2013/10/27 19:38] – mcmaster
+++ carrier:th [2025/08/04 21:23] (current) – external edit 127.0.0.1
@@ Line 19: / Line 19: @@
-====== Single inline (SIL) package ======
+====== Single inline package (SIP) ======
-====== Dual inline (DIP) package ======
+Usually resistor networks but also used for soldered modules/cards and ocassionally ICs.
+Ceramic SIP:
+{{:carrier:csip:fujitsu_edh4464-15_top.jpg?300|}}
+{{:carrier:csip:fujitsu_edh4464-15_bot.jpg?300|}}
+{{:carrier:csip:fujitsu_edh4464-15_side.jpg?200|}}
+====== Dual inline package (DIP) ======
 ===== Plastic DIP (PDIP) =====
@@ Line 36: / Line 45: @@
 {{carrier:pdip:fd1791-b01_top.jpg?300}}
 {{carrier:pdip:fd1791-b01_bot.jpg?300}}
+An unusual PDIP which doesn't fully encapsulate the leadframe:
+{{:carrier:pdip:intersil_icm7217aipi_top.jpg?300|}}
+{{:carrier:pdip:intersil_icm7217aipi_bot.jpg?300|}}
+{{:carrier:pdip:intersil_icm7217aipi_side.jpg?200|}}
 One major disadvantage of PDIPs is their relatively poor heat conduction being made primarily of glass.  A 0.3" PDIP-14 with heatsink:
@@ Line 46: / Line 61: @@
 {{carrier:pdip:dale_top.jpg?300}}
 {{carrier:pdip:dale_bot.jpg?300}}
-{{carrier:pdip:dale_side.jpg?300}}
+{{carrier:pdip:dale_side.jpg?200}}
@@ Line 58: / Line 73: @@
 {{carrier:pdip:16-1-330_top.jpg?300}}
 {{carrier:pdip:16-1-330_bot.jpg?300}}
-{{carrier:pdip:16-1-330_side.jpg?300}}
+{{carrier:pdip:16-1-330_side.jpg?200}}
@@ Line 64: / Line 79: @@
 Was popular before epoxy ("plastic") chips were made commercially viable.
@@ Line 71: / Line 88: @@
 A typical package has two fired ceramic halves with a die in a center cavity held together by glass.  Most windowed chips are of this type.
+Its unusual to have the ceramic darker on part of the chip but it does make for a nice label!  I have several that are identical (to the datecode) but does not have this black background...error during silkscreening process?
-Its unusual to have the ceramic darker on part of the chip but it does make for a nice label!  Probably part of the silkscreening process
 {{carrier:cdip:wd_wd8250cl-00_top.jpg?300}}
 {{carrier:cdip:wd_wd8250cl-00_bot.jpg?300}}
 {{carrier:cdip:wd_wd8250cl-00_side.jpg?200}}
+Erasable chips (typically EPROM but sometimes microcontrollers containing EPROM) have a quartz window:
+{{carrier:cdip:microchip_pic17c64_top.jpg?300}}
+{{carrier:cdip:microchip_pic17c64_bot.jpg?300}}
+{{carrier:cdip:microchip_pic17c64_side.jpg?200}}
@@ Line 83: / Line 105: @@
 A typical package is a single co-fired ceramic with a solderable lid.  Optional grounding strap.  These chips were more common in the 70/80s but still continue to see use in high end and military chips.  The last consumer chip I'm aware of was the Pentium 1 which used a dark purple ceramic.
+Pretty typical package:
+{{:carrier:cdip:intel_c2186-25_top.jpg?300}}
+{{:carrier:cdip:intel_c2186-25_bot.jpg?300}}
+{{:carrier:cdip:intel_c2186-25_side.jpg?200}}
+Slight variation with the grounding strap soldered directly to the lid:
+{{:carrier:cdip:ti_tms99105ajdl_top.jpg?300}}
+{{:carrier:cdip:ti_tms99105ajdl_bot.jpg?300}}
+{{:carrier:cdip:ti_tms99105ajdl_side.jpg?200}}
+An unusual package with pins to stack another chip on top (for EPROM for the MCU IIRC in this case):
+{{:carrier:cdip:nat_semi_ns87p50d-11_top.jpg?300}}
+{{:carrier:cdip:nat_semi_ns87p50d-11_bot.jpg?300}}
+{{:carrier:cdip:nat_semi_ns87p50d-11_side.jpg?200}}
+An unusual package with a lid covering the entire top:
+{{:carrier:cdip:hs_hs9378c_top.jpg?300|}}
+{{:carrier:cdip:hs_hs9378c_bot.jpg?300|}}
+{{:carrier:cdip:hs_hs9378c_side.jpg?200|}}
-=== Windowed ===
+Windowed:
 {{carrier:cdip:intel_c8751-8_top.jpg?300}}
 {{carrier:cdip:intel_c8751-8_bot.jpg?300}}
 {{carrier:cdip:intel_c8751-8_side.jpg?200}}
+Old windowed package with frosted glass (uncommon):
+{{:carrier:cdip:hitachi_hd462532_top.jpg?300}}
+{{:carrier:cdip:hitachi_hd462532_bot.jpg?300}}
+{{:carrier:cdip:hitachi_hd462532_side.jpg?200}}
@@ Line 118: / Line 169: @@
 {{carrier:cdip:white_cb2082_bot.jpg?300}}
-Very early ceramic package (1974 date code):
+Early ceramic package (1974 date code):
 {{carrier:cdip:white_fd502e_top.jpg?300}}
 {{carrier:cdip:white_fd502e_bot.jpg?300}}
+Early windowed ceramic package (window missing, 1979 date code?):
-==== Windowed ====
+{{:carrier:cdip:intel_c8702a-4_lidless_top.jpg?300}}
+{{:carrier:cdip:intel_c8702a-4_lidless_bot.jpg?300}}
-Erasable chips (typically EPROM but sometimes microcontrollers containing EPROM) have a quartz window:
+{{:carrier:cdip:intel_c8702a-4_lidless_side.jpg?200}}
-{{carrier:cdip:microchip_pic17c64_top.jpg?300}}
-{{carrier:cdip:microchip_pic17c64_bot.jpg?300}}
-{{carrier:cdip:microchip_pic17c64_side.jpg?200}}