10/100mbit SPI/parallel Ethernet controller.


44-pin QFN, decapped live.


Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.


Close-up of dense logic area at upper right:

Partial HF delayer of SRAM. Confirmed to be same process as PIC32 based on SRAM cell pitch.

azonenberg/microchip/enc424j600.txt · Last modified: 2015/01/04 22:50 (external edit)
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki