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—azonenberg:xilinx:xc9572xl [2025/08/04 21:24] (current) – external edit 127.0.0.1
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 +{{tag>collection_az vendor_xilinx type_logic type_logic/programmable type_logic/programmable/cpld year_2000 foundry_hejian tech_350nm}}
  
 +72-macrocell / 1600 gate [[vendor:xilinx|Xilinx]] [[vendor:xilinx:xc9500xl|XC9500XL series CPLD]].
 +
 +Decapped on 1/29/2014 by lab group A of CSCI 4974/6974 at RPI.
 +
 +====== Package ======
 +
 +{{:azonenberg:xilinx:dscf4619_cropped.jpg?300|}}
 +
 +====== Die ======
 +
 +Die size: 2020 x 3600 μm (7.27 mm^2)
 +
 +{{:azonenberg:xilinx:xc9572xl_bf_neo5x.jpg?600|}}
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 +{{:azonenberg:xilinx:xc9572xl_05_bf_neo40x_annotated.jpg?600|}}
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 +{{:azonenberg:xilinx:xc9572xl_06_bf_neo40x_annotated.jpg?600|}}
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 +{{:azonenberg:xilinx:xc9572xl_07_bf_neo40x_annotated.jpg?600|}}
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 +{{:azonenberg:xilinx:xc9572xl_08_bf_neo40x_annotated.jpg?600|}}