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azonenberg:xilinx:xc2c32a

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—azonenberg:xilinx:xc2c32a [2025/08/04 21:24] (current) – external edit 127.0.0.1
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 +{{tag>collection_az vendor_xilinx type_logic type_logic/programmable type_logic/programmable/cpld year_2004 tech_180nm foundry_umc}}
 +
 +[[vendor:xilinx|Xilinx]] [[vendor:xilinx:xc2c|CoolRunner-II CPLD]] with 32 macrocells. The -A version supports two I/O banks while the baseline XC2C32 only has one.
 +
 +180nm 4-metal process.
 +
 +====== Package ======
 +
 +CPG56 - 0.5mm chip-scale BGA.
 +
 +Markings:
 +  [Xilinx logo] 2C32A
 +  F40731-1049
 +  PHILIPPINES
 +  C4-AMS 6C
 +
 +{{:azonenberg:xilinx:s7303129_cropped.jpg?300|}} {{:azonenberg:xilinx:s7303130_cropped.jpg?300|}}
 +
 +====== Die overview (metal 4) ======
 +
 +Die size: 1895 x 1710 μm (3.24 mm^2)
 +
 +{{:azonenberg:xilinx:xc2c32a_bf_neo5x_annotated.jpg?600|}}
 +
 +====== Plan view closeups (metal 4) ======
 +
 +===== Die logo =====
 +
 +{{:azonenberg:xilinx:xc2c32a_03_bf_neo20x_annotated.jpg?600|}}
 +
 +===== Output bus from function block 2 macrocells to I/O bank 1 =====
 +
 +{{:azonenberg:xilinx:xc2c32a_iobus_bf_neo40x_annotated.jpg?600|}}
 +
 +===== Copyright notice (upside-down in bottom left corner) =====
 +
 +{{:azonenberg:xilinx:xc2c32a_logo_bf_neo40x_annotated.jpg?600|}}
 +
 +===== VCCIO junction =====
 +
 +Junction between VCCIO1 (left) and VCCIO2 (right) at bottom center of die. Note vias from ground ring to ground pad at bottom.
 +
 +{{:azonenberg:xilinx:xc2c32a_vcc_bf_neo40x_annotated.jpg?600|}}
 +
 +===== ZIA wiring =====
 +
 +{{:azonenberg:xilinx:xc2c32a_zia_bf_neo40x_annotated.jpg?600|}}
 +
 +====== Maps ======
 +
 +[[http://siliconprawn.org/map/xilinx/xc2c32a/mz_ns50xu/|Top metal (NS50xU)]]
 +
 +[[http://siliconprawn.org/map/xilinx/xc2c32a/stained_mit100x/|Active area Dash etch (MIT100x)]]
 +
 +[[http://siliconprawn.org/map/xilinx/xc2c32a/lap4-04_mit20x/|Poly (MIT20x)]]
 +
 +[[http://siliconprawn.org/map/xilinx/xc2c32a/|Various intermediate laps, browse around]]
 +
 +====== Cross sections ======
 +
 +{{:azonenberg:xilinx:xc2c32a_10kv_20x_6e-10a_19mm_ap4_se_01.jpg?600|}}
 +
 +{{:azonenberg:xilinx:xc2c32a_xc_01_df_neo5x_annotated.jpg?600|}}
 +
 +{{:azonenberg:xilinx:xc2c32a_xc_02_df_neo10x_annotated.jpg?600|}}
 +
 +{{:azonenberg:xilinx:xc2c32a_xc_03_df_neo20x_annotated.jpg?600|}}
 +
 +{{:azonenberg:xilinx:xc2c32a_xc_04_df_neo40x_annotated.jpg?600|}}