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azonenberg:xilinx:xc2c32a

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azonenberg:xilinx:xc2c32a [2014/02/02 23:06] – azonenbergazonenberg:xilinx:xc2c32a [2015/01/04 22:50] (current) – external edit 127.0.0.1
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 {{tag>collection_az vendor_xilinx type_logic type_logic/programmable type_logic/programmable/cpld year_2004 tech_180nm foundry_umc}} {{tag>collection_az vendor_xilinx type_logic type_logic/programmable type_logic/programmable/cpld year_2004 tech_180nm foundry_umc}}
  
-CoolRunner-II CPLD with 32 macrocells. The -A version supports two I/O banks while the baseline XC2C32 only has one.+[[vendor:xilinx|Xilinx]] [[vendor:xilinx:xc2c|CoolRunner-II CPLD]] with 32 macrocells. The -A version supports two I/O banks while the baseline XC2C32 only has one.
  
 180nm 4-metal process. 180nm 4-metal process.
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 ====== Die overview (metal 4) ====== ====== Die overview (metal 4) ======
  
-{{:azonenberg:xilinx:xc2c32a_bf_neo5x_cropped.jpg?600|}} +Die size: 1895 x 1710 μm (3.24 mm^2)
- +
-====== Floorplan (metal 4) ======+
  
 {{:azonenberg:xilinx:xc2c32a_bf_neo5x_annotated.jpg?600|}} {{:azonenberg:xilinx:xc2c32a_bf_neo5x_annotated.jpg?600|}}
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 ====== Maps ====== ====== Maps ======
  
-[[http://siliconpr0n.org/map/xilinx/xc2c32a/top_metal_ns50xu/|Top metal (NS50xU)]]+[[http://siliconpr0n.org/map/xilinx/xc2c32a/mz_ns50xu/|Top metal (NS50xU)]]
  
 [[http://siliconpr0n.org/map/xilinx/xc2c32a/stained_mit100x/|Active area Dash etch (MIT100x)]] [[http://siliconpr0n.org/map/xilinx/xc2c32a/stained_mit100x/|Active area Dash etch (MIT100x)]]
azonenberg/xilinx/xc2c32a.1391382366.txt.gz · Last modified: 2014/02/02 23:06 by azonenberg