Differences

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--- azonenberg:cypress:cy8c4245axi [2014/06/11 03:35] – azonenberg
+++ azonenberg:cypress:cy8c4245axi [2025/08/04 21:24] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
-{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_unknown}}
+{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm foundry_cypress}}
-PSoC 4200 series device.
+PSoC 4200 series device originally made on Cypress's [[http://www.cypress.com/?docID=45736|S8 SONOS process]] in the Minnesota fab (Fab 4, S8DIN-5R). GSMC in China has also licensed the S8 process technology; traceability markings presumably tell where the device came from but this isn't known yet.
   * Cortex-M0 CPU at up to 48 MHz
@@ Line 10: / Line 10: @@
   * 4 Universal Digital Blocks (UDBs, basically CPLD function blocks)
-Looks like 130 nm or smaller tech with >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending.
+Confirmed by SEM imaging to be 130nm tech, layer count not measured.
+Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending.
+====== Stackup from change notice 145273 (TODO: Measure against actual die) ======
+Ti/AlCu/TiW to Ti/TiN/AlCu/Ti/TiN for metallization in fab 4 (except for top layers)
+  * Metal 1: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN
+  * Metal 2: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN
+  * Metal 3: 500A TiW/21,250A Al 0.5% Cu/300A TiW
+Passivation: 1000A TEOS/9000A Si3N4
+Gate stack: SiO2 / 110A & SiO2 / 32A
 ====== Package ======
@@ Line 26: / Line 40: @@
 ====== Die ======
+===== Top metal =====
 Size is approximately 2120 x 3210 μm (6.80 mm<sup>2</sup>)
@@ Line 50: / Line 66: @@
 {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_25_bf_neo40x_annotated.jpg?600|}}
+===== Active area =====
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_bf_neo10x_2k_annotated.jpg?600|}}
+Boot ROM
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_19_bf_neo40x_annotated.jpg?600|}}
+I/O cell
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_20_bf_neo40x_annotated.jpg?600|}}
+NOR Flash. Interesting structure, haven't seen this before.
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_21_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_01.jpg?600|}}
+Random logic
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_22_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_02.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_03.jpg?600|}}
+Mysterious small SRAM blocks... FIFOs?
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_23_bf_neo40x_annotated.jpg?600|}}
+UDB area
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_03_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_07.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_08.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_09.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_10.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_11.jpg?600|}}
+SRAM block. Single port 6T cells.
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_04_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_05.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_06.jpg?600|}}
+Analog block. Comparator?
+{{:azonenberg:cypress:cy8c4245axi:psoc4_13.jpg?600|}}
+More random memory. Looks like a different 6T cell, possibly another IP library?
+{{:azonenberg:cypress:cy8c4245axi:psoc4_14.jpg?600|}}