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Branded vendor | Branded ID | Process | Die ID |
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B4129AJ Tsutsuji Fujitsu CG24 Cell Library
Patent US4661815 describes the architecture and customization method for those chips. They're made of predefined i/o structures framing multiple columns of double CMOS transistor pairs called “Basic cells” (BC), spaced by empty columns for routing.
Customization is done by connecting the transistors with metal to form standard logic cells, which are then connected together and to the i/o structures.
All pictures are from 315-5674.
One trace for input, and two individual traces for the N and P power transistors to allow tri-stating.
Top input is output level, bottom input is enable. Outputs go to the pin structure transistors. Described page 10 of the MBCG25512 datasheet. Uses 5 BCs.