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With a calibration slide, looking at the 0.01mm line target, I measured 423 +/- 3 pixels over 5 lines, yielding 118 +/- 1 nm per pixel.
This project seeks to document 54xx/74xx-series logic chips and subfamilies by imaging their dies and tracing out their schematics. The project started around March 2017.
Number | Function | 54xx Inventory | 74xx Inventory |
---|---|---|---|
00 | quad 2-input NAND gate | -,AS,S |
Variant | Vendor | Date code | Page link | Schematic |
---|---|---|---|---|
5400 | National Semiconductor | 8838 | page | sch |
54AS00 | Texas Instruments | 8747 | page | sch |
54S00 | Signetics | 8716 | page | sch |