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PSoC 4200 series device.
- Cortex-M0 CPU at up to 48 MHz
- 32 KB flash
- 4 KB SRAM
- 36 GPIO pins (4 ports of 8 pins plus one half-port of 4 pins)
- 2 comparators
- 4 Universal Digital Blocks (UDBs, basically CPLD function blocks)
Looks like 130 nm or smaller tech with >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison with CoolRunner-2 architecture is pending.
Package
44-pin TQFP.
Markings:
(Cypress logo) CY8C4245AXI- 483 TWN1401 A 01 D01B845 (small square) C
Die
Size is approximately 2120 x 3210 μm (6.80 mm2)
Overview
Logo and alignment marks in upper left corner. Note part number “8C44200A” as opposed to the official part number “8C4245AXI”
Random vertical interconnect routing on top metal. Smallest observed top metal half-pitch is 1.6 μm (1.7 μm wire, 1.5 μm space). This is very coarse compared to the lower metal layers… either this is a deep-submicron process with thick top metal for power, or they just want low resistance on the top layer for long-range routing of analog signals with minimal losses.
Random horizontal interconnect on Mtop-1. Half-pitch appears to be around 320 nm which is typical x1 pitch for the 180 nm node. Since this is an upper layer the technology node is likely even smaller, perhaps 130 nm. There is at least one vertical routing layer visible below this, and possibly more routing layers before M1 (which isn't visible). Closeup is cropped from full image with contrast boosted.
Same region of die with focal plane on Mtop-2.
