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| process_tech [2013/10/20 14:59] – external edit 127.0.0.1 | process_tech [2015/12/17 22:52] (current) – [Eight or more layers] azonenberg |
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| ===== Cheesing / bamboo structures ===== | ===== Cheesing / bamboo structures ===== |
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| Copper processes will typically include "cheesing" or a "bamboo structure" - small rectangular cutouts in large power buses - because copper is more susceptible to electromigration than aluminum is (see [[http://en.wikipedia.org/wiki/Electromigration#Bamboo_structure_and_metal_slotting|Wikipedia article on electromigration]]). Since mass transport in electromigration typically occurs parallel to grain boundaries, the rate of mass transport can be dramatically reduced by making the wire width smaller than the grain size so that grain boundaries are largely perpendicular to the direction of current flow. As a result, the presence of these structures can be used as a very strong hint that the process is copper based. | Modern processes will typically include "cheesing" or a "bamboo structure" - small rectangular cutouts in large power buses (see [[http://en.wikipedia.org/wiki/Electromigration#Bamboo_structure_and_metal_slotting|Wikipedia article on electromigration]]). Since mass transport in electromigration typically occurs parallel to grain boundaries, the rate of mass transport can be dramatically reduced by making the wire width smaller than the grain size so that grain boundaries are largely perpendicular to the direction of current flow. As a result, the presence of these structures can be used as a hint that the trace in question carries high current. |
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| FIXME: Is this backwards? Some aluminum stuff uses bamboo too. | Xilinx CoolRunner-II CPLD (180nm aluminum, 4 metal layers) |
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| Xilinx CoolRunner-II CPLD (180nm copper, 4 metal layers) | |
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| {{::azonenberg:process_examples:copper_power_rail.jpg?400|}} | {{::azonenberg:process_examples:copper_power_rail.jpg?400|}} |
| Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing. | Many dense interconnect layers, as with 4-7 layer devices, but with the addition of a dedicated power layer (or layers) on top metal for improved power distribution performance and to avoid cluttering high-density interconnect layers with power busing. |
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| Example image (Xilinx XC6SLX4, 45nm Samsung process, probably ~12 layers). Top metal wires are massive, at least 5μm. | Example image (Xilinx XC6SLX4, 45nm Samsung process, 9 layers). Top metal wires are massive, at least 5μm. |
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| {{:azonenberg:process_examples:topmetal_power.jpg?600|}} | {{:azonenberg:process_examples:topmetal_power.jpg?600|}} |
