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—memory:sram [2025/08/04 21:23] (current) – external edit 127.0.0.1
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 +====== RSA SecurID example ======
 +
 +===== Raw images =====
 +
 +From top to bottom
 +
 +{{:mcmaster:memory:sram:securid:m2_img.png?300|}}
 +
 +{{:mcmaster:memory:sram:securid:lapped_img.png?300|}}
 +
 +{{:mcmaster:memory:sram:securid:poly_img.png?300|}}
 +
 +{{:mcmaster:memory:sram:securid:active_img.png?300|}}
 +
 +
 +===== Processed =====
 +
 +{{:mcmaster:memory:sram:securid:faded.png?300|}}
 +
 +{{:mcmaster:memory:sram:securid:ul.png?300|}}
 +
 +{{:mcmaster:memory:sram:securid:sram_schematic.png|}}
 +
 +
 +====== References ======
 +
 +  * ICE Shared Construction Analysis SCA
 +    * 9412-394 (Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM): http://smithsonianchips.si.edu/ice/cd/9412_394.pdf
 +    * 9609-511 (UMC UM613264F-7 2Mbit SRAM): http://smithsonianchips.si.edu/ice/cd/9609_511.pdf
 +    * 9612-512 (Samsung KM984000ALG-7 4 Meg. SRAM): http://smithsonianchips.si.edu/ice/cd/9612_512.pdf
 +    * 9612-523 (Sony CXK5B16120J-12 1Mbit (64K x 16) BiCMOS SRAM): http://smithsonianchips.si.edu/ice/cd/9612_523.pdf
 +    * 9703-499 (Mosel Vitelic MS622656CLL-70PC 256Kbit SRAM): http://smithsonianchips.si.edu/ice/cd/9703_499.pdf