The LeCroy Model 4291 B is a single-width CAMAC module containing 32 time digitizers. Two 34-pin front-panel connectors (Pl, P2), each accommodating 16 complementary inputs at ECL levels, allow use of twisted-pair ribbon cables from the discriminator outputs to the TDC's. The input impedance of the digitizers is 110 Ohm.
Each digitizer consists of one LSI Custom Monolithic Model MTD110. This monolithic circuit has been expressly designed to provide excellent time resolution in applications where a large number of digitizers are required. It is a 9-bit plus overflow time-to-digital converter utilizing an analog time stretcher followed by a digital counter. The outstanding feature of this analog device is its self-calibration mode AUTOTRIM). This feature employs two sets of internal registers, DAC's, and digital comparators used to adjust both the offset and the slope of the analog ramp. In AUTOTRIM mode, a precision pulse source (in the 4298 Controller) generates a series of pulses that alternate between a pedestal count of two and a full scale count of 514 (overflow plus 2). The initial MTD110 registers are then appropriately updated causing perfect calibration to be achieved. The adjustment range corrects for unit-to-unit variations in manufacturing, as well as, slow temperature and/or voltage changes. The range of the offset adjusts is more than adequate for internal variations, and allows for the option of correcting for external cable and preamplifier variations. All of the active circuits are incorporated in a single, low-power, 18-pin DIP package, making it possible to achieve high accuracy and high density at low per-channel cost.
The 4291 offers either a COMMON START or COMMON STOP operating mode, user selected via the Model 4298 Crate Controller.
In the COMMON STOP mode, the Wire input to the differential receiver becomes the Start input. This begins the timing cycle, which is completed by receipt of an EXPeriment COMmon trigger (derived from the event trigger) which generates a Stop. Subsequent Wire inputs before the trigger are each processed as another Start, just as if the System were quiescent. After the trigger pulse is received, the inputs are inhibited and the arrival time of the last Wire input pulse before the trigger (but within the full scale time range) is digitized and transferred to the 4298 Controller. The mode is ideal when a quality pretrigger is not available since the entire full scale time can be used as the trigger decision time.
In the COMMON START mode, the EXPeriment COMmon trigger generates a Start used to initiate the timing cycle. Then the first Wire input received (during the full scale time) causes a Stop, and the timing cycle is completed. At the end of the full scale time, the conversion and transfer cycle is initiated.
In either mode, if a wire pulse is received during the full scale time, a HIT register will be set to provide a prompt indication of valid data. This HIT data is used internally to reduce readout time (only HIT modules are read out) and is available to the user via a rear panel connector for use in the higher level trigger logic.
In the Model 4291B, the hit registers are buffered and available in parallel on connector P3 located at the top rear end of the unit. The tristate TTL buffers, which are of negative-type logic, can be strobed via the ENABLE input of P3. A positive logic option is available upon request.
INPUT/OUTPUT SPECIFICATIONS
| Hit Register Outputs: | 32-bit parallel output provides low-power Schottky, low-true tristate output. |
| Output Enabled, No Hit: | > 2.4 V at + 15 mA max. |
| Output Enabled, Hit Present: | < 0. 5 V at - 24 mA max. |
| Output Not Enabled: | High impedance; +/- 20 uA. |
| Enable Input: | High level disables (> 2 V, 0.1 mA max.). Low level enables (< 0.8 V, 0.4 mA max.). Enable time < 40 nsec. Data are available after the full scale time until reset. |
| P3 Connector: | Rear panel 32-pin connector mates with same connectors as used on front panel. Detailed pin allocation is defined in the 4291 B User Manual. |
| SPECIFICATIONS | |
| Inputs: | 32 ECL differential line receivers; 110 Ohm input impedance; double-pulse resolution < 200 nsec in COMMON STOP mode (not applicable in COMMON START mode); 50 nsec minimum width. |
| Full Scale: | Continuously adjustable from 512 to 2048 nsec (1 nsec/count to 4 nsec/count). Other options available on request. |
| Accuracy: | Gain accuracy within 0. 1 % with absolute accuracy within 1 count. |
| TDC Range: | 9 bits plus overflow. |
| Common Trigger: | Distributed by 4298 module via the CAMAC Dataway. In the COMMON START mode, the trigger must be supplied 200 nsec before the last expected wire pulse. In the COMMON STOP mode, the trigger must be supplied 200 nsec after the first expected wire pulse. |
| Pedestal Compensation: | External channel-to-channel variations in Wire input timing of up to +/- 5% of full scale time may be automatically compensated by the AUTOTRIM feature. (Requires that 4298 test pulses be supplied at the detector.) |
| Conversion and Transfer Time: | Approximately 35 ,sec plus 12 usec per "HIT" module plus 0.5 usec per valid word (for 5-meter DATABUS). |
| Reset (Fast Clear): | Distributed by 4298 module via the CAMAC Dataway. Resets TDC's and HIT registers in less than 300 nsec. |
| Readout Control: | Requires one Model 4298 module and one 4299 DATABUS Interface. All
clocks, controls, test pulses, and data are bused via the CAMAC Dataway.
Trigger Decision Logic HIT pattern is available on upper rear connector P3 of CAMAC module. |
| Outputs: | NOTE: A HIT is registered by any wire input occurring within the digitized time window plus a 10 to 20 percent extension on either end of this window. |
| Input Connectors: | Two lock and eject dual 17-pin headers. Mates with 3M 3414-6034, AMP 86987-1, or LeCroy CK/34. Pin assignments are listed in the User Manual. Cable should be 34 conductor twisted pair ribbon, Spectrastrip 455-248-34 or LeCroy DC2/24-xx cable with connectors . |
| Current Requirements: | +24 V at 30 mA
- 6 V at 900 mA + 6 V at 700 mA |