LeCroy 2376A ECLine Data Array

* Stores hit addresses
* 20 MHz store/search rates
* Up to 15 addresses searched simultaneously
* ECLine/ECL port compatible
* Ideal for track finders
* Fast clear

The Model 2376A Data Array is a single width CAMAC Module for use as a building block in fast on-line track finding devices. It is a member of the family of ECLine data handler modules.

FUNCTIONAL DESCRIPTION

One of the tasks of a track finder is to verify the presence of data, i.e., "hits", in one region of a detector that are predicted by another part of the apparatus. A simple example is the verification of hits in areas of the second or third plane of a 3-plane wire chamber that are predicted from hits in the first plane and knowing the origin (interaction vertex).

Prediction/verification are performed by the Model 2376 in a Load and Search sequence. In the Load Sequence, addresses of hit wires (or pads) are presented to the Load input of the Model 2376 and stored in the internal data memory of the module. The module has a range of 1024 addresses. The upper 3 bits of the dataword may be used by the Load Steering Logic to accept or reject the load strobe. A side-panel switch permits each of the eight possibilities to be separately enabled. This allows the Data Array to be loaded with one type of data (e.g., "x" or plane 1) while ignoring another type (e.g., "y" or plane 2).

In the Search Sequence, a range of addresses defined by a Search Address and a Search Width is tested for hits. If any hits fall within a pre-defined search range, a Status Bit is set. The 3-bit Search Width can be dynamically controlled by the front panel Search Width input or by CAMAC.

The Search process may be repeated for any Search Address range (within the limit of the address space) presented to the Search Address Input of the module.

A track finder can be constructed from several ECLine data handler modules. Usually LeCroy Model 2375 Data Stack modules are used to sequence through all combinations of hits in several chamber planes. When valid pairs are found, a corresponding region of another plane may be searched using the Model 2376. For detailed examples, see LeCroy Application Note 24A and Publication P11.

SPECIFICATIONS

NEEDED CAMAC COMMANDS

Access Control (Data Array)

F(16) A(0)

Write Address and Search Width and/or Steering Bits (Disable Steering Bits if CAMAC does not use)

F(16) A(2)

Search, Q=1 response if address was previously loaded

F(16) A(1)

Load

F(24) A(0)

Enable Front Panel

F(26) A(0)

Enable CAMAC

F(26) A(3)

Enable CAMAC and Front Panel

F(26) A(1)

Enable Steering Bits

F(24) A(1)

Disable Steering Bits

F(26) A(2)

Enable Wraparound

F(24) A(2)

Disable Wraparound

Initialization Control

F(9) A(0)

Master Reset

Access Control (Board)

F(0) A(0)

Read Address and Status Bit

F(0) A(1)

Read Steering Bits and Steering Bit Switch Settings

Note: All function Codes F(i) A(i) require a valid N.

ECL INPUTS

Master Reset (MRST):

Front panel differential ECL input via a two-pin connector, resets the .contents of all data addresses to "0". The SSTB and LSTB must be logic "0".

Load Strobe (LSTB):

Front panel differential ECL input via a two-pin connector. Writes a "1" to the address presented at the Load Address input if Steering Bits match side panel switch settings. The SSTB must be "0". For 20 MHz operation, the LSTB must have a width of 15 +/- 2 nsec.

Load Strobe Enable (LSTE):

Front panel differential ECL input via a two-pin connector, enables Load Strobe if ECL logic "1". A logical "0" disables Load Strobe. When unconnected, it is a logical "1" and LSTB is enabled.

Load Address (LA), Steering Bits:

Front panel differential ECL input for the Address and Steering Bits. Supplied via an ECLine standard 17-pair header. The Address must be stable simultaneously with the application of the LSTB.

Search Strobe (SSTB):

Front panel differential ECL input on a two-pin connector. Reads Search Address Input and outputs the Status Bit. The LSTB must be logic "0". For 20 MHz operation, the SSTB must have a width of 15+2 nsec.

Search Strobe Enable (SSTE):

Front panel differential ECL input via a two-pin connector, enables Search Strobe if ECL logic "1". A logical "0" disables Search Strobe. When unconnected, it is a logical "1" and SSTB is enabled.

Search Address Input (SA), Search Width:

Front panel differential ECL input accepting 10-bit Address input and 3-bit Search Width input for dynamical Search Width control. Supplied via an ECLine standard 17-pin header.

All Data In (ADI):

Front panel differential ECL input via two-pin connector to signify that loading of addresses is complete and issue LC output. After ADI, the Load Strobe is disabled until the next MRST. When unused, it is set to a logical "1" condition. An ADI ("0") suspends response to a read request.

ECL OUTPUTS

Status Bit (STAT):

Status bit is true if at least one hit is present within the Search Width.

Status Bit Ready (SBR):

Status Bit Ready (SBR): Pulse of 30 nsec duration, leading edge arrives when STAT is ready for reading.

Load Address Complete (LAC):

Front panel differential ECL output via a two-pin connector to indicate the completion of a write operation.

Search Address Complete (SAC):

Front panel differential ECL output via a two-pin connector, indicates that the read operation is complete and that the Status Bit is valid.

Loading Complete (LC):

Front panel differential ECL output, set to ECL logic "1" after ADI and reset to ECL "0" by MRST. For use in pipelined trigger processors to initiate searching after loading is complete.

Note: All inputs are ECLine Standard terminated in 112 Ohm and convertible to high impedance by removing the termination resistor pack (SIP).

SPECIFICATIONS

Data Rate:

DC to 20 MHz.

Load and Search Address Size:

10 bits (1024 addresses).

Steering Bits:

3 bits, input via front-panel Load Address connector, or CAMAC that are compared to the steering switch settings. Permits module to ignore data with non-matching steering bits.

Search Width:

3 bits, set via front panel Search Address connector or CAMAC (0 to +/-7 positions from center).

Power Requirements:

+6 V, 24 W maximum.

Packaging:

In conformance with CAMAC Standard for nuclear modules (ESONE Committee Report EUR4100 or the IEEE-583 Standard). RF-shielded single width CAMAC module.

Glossary of Terms:

MRST Master Reset - Input
SA Search Address - Input
SW Search Width - Input
SSTB Search Strobe - Input
SAC Search Address Complete - Output
LA Load Address - Input
LSTB Load Strobe - Input

LAC Load Address Complete - Output
AD I All Data In - Input
LC Load Complete - Output
LSTE Load Strobe Enable - Input
SSTE Search Strobe Enable - Input
SBR Status Bit Ready - Output
STAT Status Bit - Output

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SPECIFICATIONS
NEEDED CAMAC COMMANDS
Access Control (Data Array)
F(16) A(0)	Write Address and Search Width and/or Steering Bits (Disable Steering Bits if CAMAC does not use)
F(16) A(2)	Search, Q=1 response if address was previously loaded
F(16) A(1)	Load
F(24) A(0)	Enable Front Panel
F(26) A(0)	Enable CAMAC
F(26) A(3)	Enable CAMAC and Front Panel
F(26) A(1)	Enable Steering Bits
F(24) A(1)	Disable Steering Bits
F(26) A(2)	Enable Wraparound
F(24) A(2)	Disable Wraparound
Initialization Control
F(9) A(0)	Master Reset
Access Control (Board)
F(0) A(0)	Read Address and Status Bit
F(0) A(1)	Read Steering Bits and Steering Bit Switch Settings
Note: All function Codes F(i) A(i) require a valid N.
ECL INPUTS
Master Reset (MRST):	Front panel differential ECL input via a two-pin connector, resets the .contents of all data addresses to "0". The SSTB and LSTB must be logic "0".
Load Strobe (LSTB):	Front panel differential ECL input via a two-pin connector. Writes a "1" to the address presented at the Load Address input if Steering Bits match side panel switch settings. The SSTB must be "0". For 20 MHz operation, the LSTB must have a width of 15 +/- 2 nsec.
Load Strobe Enable (LSTE):	Front panel differential ECL input via a two-pin connector, enables Load Strobe if ECL logic "1". A logical "0" disables Load Strobe. When unconnected, it is a logical "1" and LSTB is enabled.
Load Address (LA), Steering Bits:	Front panel differential ECL input for the Address and Steering Bits. Supplied via an ECLine standard 17-pair header. The Address must be stable simultaneously with the application of the LSTB.
Search Strobe (SSTB):	Front panel differential ECL input on a two-pin connector. Reads Search Address Input and outputs the Status Bit. The LSTB must be logic "0". For 20 MHz operation, the SSTB must have a width of 15+2 nsec.
Search Strobe Enable (SSTE):	Front panel differential ECL input via a two-pin connector, enables Search Strobe if ECL logic "1". A logical "0" disables Search Strobe. When unconnected, it is a logical "1" and SSTB is enabled.
Search Address Input (SA), Search Width:	Front panel differential ECL input accepting 10-bit Address input and 3-bit Search Width input for dynamical Search Width control. Supplied via an ECLine standard 17-pin header.
All Data In (ADI):	Front panel differential ECL input via two-pin connector to signify that loading of addresses is complete and issue LC output. After ADI, the Load Strobe is disabled until the next MRST. When unused, it is set to a logical "1" condition. An ADI ("0") suspends response to a read request.
ECL OUTPUTS
Status Bit (STAT):	Status bit is true if at least one hit is present within the Search Width.
Status Bit Ready (SBR):	Status Bit Ready (SBR): Pulse of 30 nsec duration, leading edge arrives when STAT is ready for reading.
Load Address Complete (LAC):	Front panel differential ECL output via a two-pin connector to indicate the completion of a write operation.
Search Address Complete (SAC):	Front panel differential ECL output via a two-pin connector, indicates that the read operation is complete and that the Status Bit is valid.
Loading Complete (LC):	Front panel differential ECL output, set to ECL logic "1" after ADI and reset to ECL "0" by MRST. For use in pipelined trigger processors to initiate searching after loading is complete.
Note: All inputs are ECLine Standard terminated in 112 Ohm and convertible to high impedance by removing the termination resistor pack (SIP).
SPECIFICATIONS
Data Rate:	DC to 20 MHz.
Load and Search Address Size:	10 bits (1024 addresses).
Steering Bits:	3 bits, input via front-panel Load Address connector, or CAMAC that are compared to the steering switch settings. Permits module to ignore data with non-matching steering bits.
Search Width:	3 bits, set via front panel Search Address connector or CAMAC (0 to +/-7 positions from center).
Power Requirements:	+6 V, 24 W maximum.
Packaging:	In conformance with CAMAC Standard for nuclear modules (ESONE Committee Report EUR4100 or the IEEE-583 Standard). RF-shielded single width CAMAC module.
Glossary of Terms:	MRST Master Reset - Input SA Search Address - Input SW Search Width - Input SSTB Search Strobe - Input SAC Search Address Complete - Output LA Load Address - Input LSTB Load Strobe - Input LAC Load Address Complete - Output AD I All Data In - Input LC Load Complete - Output LSTE Load Strobe Enable - Input SSTE Search Strobe Enable - Input SBR Status Bit Ready - Output STAT Status Bit - Output