LeCroy 2259A 12 Channel PK Sensing ADC

CAMAC Model 2259A 12-Channel, 11-Bit Peak-Sensing Analog-to-Digital Converter

The Model 2259A 12-Channel CAMAC ADC is based largely on the design of the widely used Model 2249W. Digital sections are identical, utilizing the same synchronized oscillator circuit and low-power LeCroy Model SC-100 Hybrid scaler section, directly interchangeable in either ADC. The analog front end of the 2259A is the LeCroy Model VT-100C Voltage-to-Time Con- verter, offering superior linearity and stability over previous versions.

The Model 2259A accepts negative-going analog inputs up to -2 volts in amplitude within its linear dynamic range, giving an 11-bit digital output proportional to the highest point of the pulse falling within an externally applied gate interval. The resultant ADC sensitivity is approx- imately -1 mV/count. The analog input signal should have at least a 100 nsec risetime, or total FWHM duration from 200-400 nsec. The minimum recommended gate duration is 100 nsec, and should enclose the negative peak of the input pulse. Digitizing time of the 2259A is fixed at 106 usec. However, for lower resolution applications, this time may be factory-adjusted downward.

In common with all new LeCroy CAMAC data acquisition modules, the 2259A offers a fast clear input (< 2 usec total clearing time) to permit fast rejection of unwanted data before, during, or after conversion is complete, eliminating the need for long analog delays. In addi- tion, a front-panel test feature permits on-line testing of the entire ADC circuit. When F25 is applied, the 2259A generates an internal 100 nsec gate at S2 time. If the CAMAC I is present, the front panel "Test" input will inject a signal with a proportionality constant of -0.167 volt/volt into all inputs. If I is not present, the "Test" input is disabled; F25 will generate the internal gate at S2, but only the residual pedestal at that gate width will be measured.

The Model 2259A responds to the CAMAC Functions FO,F2,F8,F9,F1O,F24,F25, and F26, and accepts or generates the following CAMAC commands: Z or C, I,Q,X,L. Packaging of the 2259A is a #1 width CAMAC module, conforming to IEEE Report #583. Current usage is low enough to permit the use of up to 23 2259A's (276 channels) in a single, standard, powered CAMAC crate.

SPECIFICATIONS Model 2259A 12-CHANNEL PEAK-SENSING ADC

Analog Inputs:

Twelve; Lemo-type connectors; voltage-(peak) sensing; direct-coupled, quiescently at approximately +0.5 mV; 50 Ohm impedance (optional 500 Ohm); protected to +/- 100 volts against 1 usec transients; accepts either negative-going "tail" pulses of ~100 nsec risetime and -200 nsec falltime, or bipolar pulses of 300 to 400 nsec total duration.

Full-Scale Range:

-2 volts.

Full-Scale Uniformity:

+/-5%.

Integral Linearity:

Smooth curve within +/- 4 counts of best straight line. Some dependence on input pulse shape.

ADC Resolution:

1980 counts (~0.05%).

Long-Term Stability:

Better than 0.25% of reading +/- 4 mV/week (at constant temperature).

Temperature Coefficient:

Typical, 0; max., +/-0.03%/'C of full scale.

ADC Isolation:

A -5 volt, 100 nsec overload pulse in any one ADC disturbs data in any other ADC by no more than 2 mV.

Gate Input:

One gate common to all ADC's; Lemo-type connectors; 50 Ohm impedance; -600 mV or greater enables; minimum duration, 100 nsec; effective opening and closing times, 2 nsec; internal delay, 2 nsec; must enclose negative peak of input pulse; maximum duration, 2 usec.

Fast Clear:

One front-panel input common to all ADC's, Lemo-type connector; 50 Ohm impedance; -600 mV or greater clears, minimum duration, 50 nsec. (Caution: narrower pulses cause partial clearing). Requires additional 2 usec settling time after clear.

Residual Pedestal:

Typically 6 counts.

Test Function:

With CAMAC I present, the positive DC level applied to front panel "Test" input (internal high impedance connection to + 12 volts) or optional rear connector P1, P2, or P5 patch points will inject signal with a proportionality constant of -0. 1 67 volt/volt into all inputs at F(25) -S2 time. (With CAMAC I not present, F(25)-S2 will generate ~100 nsec gate only, providing a measure of residual pedestal only.)

Digitizing Time:

106 usec. By factory option, fewer-bit operation for shorter conversion time.

Readout Time:

Readout may proceed at the fastest rate permitted by the CAMAC standard after digitization is complete.

Readout Control:

Ready for readout when LAM signal appears. Refer to ESONE Committee Report EUR4100e and EUR4600e for additional timing details, voltages, logic levels, impedances, and other standards. (Also IEEE Report #583.)

Data:

The proper CAMAC function and address command normally gates the 11 binary bits of the selected channel onto the R1 to R11 (20 to 210) Dataway bus lines.

CAMAC Commands:

Z or C:

ADC's and LAM are cleared by the CAMAC "Clear" or "Initialize" command; requires S2.

1:

Gate input is inhibited during CAMAC "Inhibit" command. (Test Function is enabled.)

Q:

A Q=l response is generated in recognition of an F(O) or F(2) Read function or an F(8) function if LAM is set for a valid "N" and "A", but there will be no response (Q=O) under any other condition. The Q response for empty modules can be suppressed. (See Q and LAM suppression.)

X:

An X=1 (Command Accepted) response is generated when a valid F, N and A command is generated.

L:

A Look-At-Me signal is generated from end of conversion until a module Clear or Clear LAM. LAM is disabled for the duration of N, can be permanently enabled or disabled by the Enable and Disable function command, and can be tested by Test LAM. Standard option causes LAM to be suppressed for empty modules.

CAMAC Function Codes:

F(O):

Read registers; requires N and A. A(O) through A(11) are used for channel addresses.

F(2):

Read registers and Clear modules and LAM; requires N and A; (Clears on A(11) only.)

F(8):

Test LAM; requires N and any A from A(O) to A(11) independent of Disable LAM. 0-response is generated if LAM is set.

F(9):

Clear module and LAM; requires N, S2, and any A from A(O) to A(l 1).

F(10):

Clear LAM; requires N, S2 and any A(O) to A(11).

F(24):

Disable LAM; requires N, S2 and any A from A(O) to A(11).

F(25):

Test modules; requires N, S2 and any A from A(O) to A(11).

F(26):

Enable LAM; requires N, S2 and any A from A(O) to A(11).

Caution: The state of the LAM mask will be arbitrary after power turn-on.

Q and LAM Suppression:

Adjustable potentiometer (accessed from side of module) sets count level required (from 0 to 100) before data is considered useful. A module in which all channels contain less than set amount will produce no Q-response or LAM and appears during readout as an empty CAMAC slot, thus reducing readout time. A Command Accepted response is still generated. The LAM suppress portion can be disabled with a solder jumper option.

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Analog Inputs:	Twelve; Lemo-type connectors; voltage-(peak) sensing; direct-coupled, quiescently at approximately +0.5 mV; 50 Ohm impedance (optional 500 Ohm); protected to +/- 100 volts against 1 usec transients; accepts either negative-going "tail" pulses of ~100 nsec risetime and -200 nsec falltime, or bipolar pulses of 300 to 400 nsec total duration.
Full-Scale Range:	-2 volts.
Full-Scale Uniformity:	+/-5%.
Integral Linearity:	Smooth curve within +/- 4 counts of best straight line. Some dependence on input pulse shape.
ADC Resolution:	1980 counts (~0.05%).
Long-Term Stability:	Better than 0.25% of reading +/- 4 mV/week (at constant temperature).
Temperature Coefficient:	Typical, 0; max., +/-0.03%/'C of full scale.
ADC Isolation:	A -5 volt, 100 nsec overload pulse in any one ADC disturbs data in any other ADC by no more than 2 mV.
Gate Input:	One gate common to all ADC's; Lemo-type connectors; 50 Ohm impedance; -600 mV or greater enables; minimum duration, 100 nsec; effective opening and closing times, 2 nsec; internal delay, 2 nsec; must enclose negative peak of input pulse; maximum duration, 2 usec.
Fast Clear:	One front-panel input common to all ADC's, Lemo-type connector; 50 Ohm impedance; -600 mV or greater clears, minimum duration, 50 nsec. (Caution: narrower pulses cause partial clearing). Requires additional 2 usec settling time after clear.
Residual Pedestal:	Typically 6 counts.
Test Function:	With CAMAC I present, the positive DC level applied to front panel "Test" input (internal high impedance connection to + 12 volts) or optional rear connector P1, P2, or P5 patch points will inject signal with a proportionality constant of -0. 1 67 volt/volt into all inputs at F(25) -S2 time. (With CAMAC I not present, F(25)-S2 will generate ~100 nsec gate only, providing a measure of residual pedestal only.)
Digitizing Time:	106 usec. By factory option, fewer-bit operation for shorter conversion time.
Readout Time:	Readout may proceed at the fastest rate permitted by the CAMAC standard after digitization is complete.
Readout Control:	Ready for readout when LAM signal appears. Refer to ESONE Committee Report EUR4100e and EUR4600e for additional timing details, voltages, logic levels, impedances, and other standards. (Also IEEE Report #583.)
Data:	The proper CAMAC function and address command normally gates the 11 binary bits of the selected channel onto the R1 to R11 (20 to 210) Dataway bus lines.
CAMAC Commands:
Z or C:	ADC's and LAM are cleared by the CAMAC "Clear" or "Initialize" command; requires S2.
1:	Gate input is inhibited during CAMAC "Inhibit" command. (Test Function is enabled.)
Q:	A Q=l response is generated in recognition of an F(O) or F(2) Read function or an F(8) function if LAM is set for a valid "N" and "A", but there will be no response (Q=O) under any other condition. The Q response for empty modules can be suppressed. (See Q and LAM suppression.)
X:	An X=1 (Command Accepted) response is generated when a valid F, N and A command is generated.
L:	A Look-At-Me signal is generated from end of conversion until a module Clear or Clear LAM. LAM is disabled for the duration of N, can be permanently enabled or disabled by the Enable and Disable function command, and can be tested by Test LAM. Standard option causes LAM to be suppressed for empty modules.
CAMAC Function Codes:
F(O):	Read registers; requires N and A. A(O) through A(11) are used for channel addresses.
F(2):	Read registers and Clear modules and LAM; requires N and A; (Clears on A(11) only.)
F(8):	Test LAM; requires N and any A from A(O) to A(11) independent of Disable LAM. 0-response is generated if LAM is set.
F(9):	Clear module and LAM; requires N, S2, and any A from A(O) to A(l 1).
F(10):	Clear LAM; requires N, S2 and any A(O) to A(11).
F(24):	Disable LAM; requires N, S2 and any A from A(O) to A(11).
F(25):	Test modules; requires N, S2 and any A from A(O) to A(11).
F(26):	Enable LAM; requires N, S2 and any A from A(O) to A(11).
Caution: The state of the LAM mask will be arbitrary after power turn-on.
Q and LAM Suppression:	Adjustable potentiometer (accessed from side of module) sets count level required (from 0 to 100) before data is considered useful. A module in which all channels contain less than set amount will produce no Q-response or LAM and appears during readout as an empty CAMAC slot, thus reducing readout time. A Command Accepted response is still generated. The LAM suppress portion can be disabled with a solder jumper option.