The LeCroy Model 2229 is an Octal Time-to-Digital Converter, packaged in a single width CAMAC module. It incorporates all the advanced operating characteristics which experience has indicated necessary for accurate and reliable measurement of nanosecond time intervals. It employs the new ECLine logic standard resulting in cabling convenience and economy.
The Model 2229 has 8 independent channels, each of which measures the time from the leading edge of a Common Start pulse to the leading edge of its individual Stop pulse. Any stop pulses received before Start signal are ignored and only one Stop is accepted for every Start.
Conversion begins upon receipt of the start signal and proceeds until one of the following: a stop signal is received; the cycle is terminated by the application of a front-panel Fast Clear signal; or the TDC reaches full scale.
The 2229 converts the measured time intervals into a 11-bit digital number at the rate of 20 MHz, for a full scale digitizing time of 100 microseconds. Rear-panel control of full-scale and conversion slope permits digitization to fewer bits and a shorter conversion time if desired. The conversion clock is started in phase with the TDC start signal to assure synchronization and eliminate the inaccuracy introduced by the free- running oscillators in conventional designs. LAM, if enabled, is generated at the end of the conversion interval.
The 2229 has three switch-selectable full-scale time ranges, 100, 200, and 500 nsec, which are digitized to 95% of 11 bits (2048 channels) and provide 50, 100, and 250 psec resolutions respectively. Longer time ranges (up to 10 microseconds) may be provided on request at slight expense of stability and accuracy.
On line testing is facilitated by either a front-panel Common Stop input or F(25). A signal at the Common Stop input generates simultaneous stops for each channel, permitting accurate testing of both front end and scaler section of the module and uniform system testing and time calibration. F(25) is provided for a quick test of the front end and scaler sections with a time measurement of 80% of full scale.
In high rate or colliding beam experiments, excessive system deadtime due to false starts may be eliminated through use of the 2229's fast clear input. Accepting NIM level signals, this input allows the TDC to be cleared at any point in its conversion cycle without the necessity for any Dataway operations.
All standard LAM functions are available in the 2229 to facilitate data readout. To minimize readout time, both Q and LAM may be suppressed if the module does not contain data.
Specifications CAMAC MODEL 2229 OCTAL TIME-TO-DIGITAL CONVERTER
| Stop Inputs: | Eight, using a 2 x 8 pin connector (mates with LeCroy 403211016 or 3M 3452-6016 or equivalent); accepts differential ECL input levels; 110 Ohm input impedance pin-to-pin; direct coupled; 5 nSec minimum width; inputs ignored unless preceded by a "Start" input. |
| Common Start Input: | One, common to all channels, using a pin pair on the control group (2 x 8-pin) connec- tor (mates with LeCroy 403211016 or 3M 3452-6016 or equivalent); accepts differential ECL input levels; 112 Ohm input impedance pin to pin; direct coupled; 5 nSec minimum width. |
| Common Stop Input: | One, common to all channels, input characteristics identical to Common Stop. Func- tions identical to the individual Stop inputs above, used for on-line testing. |
| Fast Clear: | One, common to all channels, input characteristics identical to Common Stop except 50 nsec minimum width. Requires 1.4 usec after start of clear signal to settle to 1 +/- 1 counts. (However, if the unit is always cleared at a fixed time before each start, it will settle to a constant offset with a small uncertainty, effectively permitting fast reset times on the order of 500 nSec). |
| Full-Scale Time Range: | 11-bit binary output corresponds to 100, 200, and 500 nSec nominal, switch-selectable (with longest range field-adjustable up to 1 uSec). Larger full-scale possible by factory option up to 10 uSec. Both the full-scale value and conversion slope are rear-panel adjustable, permitting faster conversion at the expense of range. |
| Integral Non-linearity: | <= +/- 2 counts (20 nSec to full scale). |
| Differential Non-linearity: | Channel widths vary by <= +/- 10% (10 nSec to full scale). < +/-30% for long-range option. |
| Time Resolution: | 50 pSec on 100 nSec range; 100 pSec on 200 nSec range; 250 pSec on 500 nSec range. |
| Temperature Coefficient: | Typically (+/- 0.02% of full scale +/- 0.01% of reading) per degree C. |
| Digitizing Time: | Approximately 100 uSec for 11-bits; rear-panel adjustable for fewer bits, shorter conversion time. |
| Readout Time: | Readout may proceed at the fastest rate permitted by the CAMAC standard after digitiz- ing is complete. |
| Test Functions: | An internal start/stop is generated with approximately 80% of full scale time in response to an F(25) command. On-line testing and calibrations can be done with common start and common stop above. |
| Data: | The proper CAMAC function and address command gates the binary data of the selected channel onto the R(1) to R(11) (2^0 to 2^10) Dataway bus lines. The full-scale number of bits, and thus the conversion time, can be selected by a rear-panel pot and test point. The overflow flag is always presented on R(12). |
| CAMAC Commands: | |
| Z or C: | All registers are simultaneously cleared by the CAMAC "Clear" or "Initialize" command. Requires "S2" |
| 1: | "Start" input is inhibited during CAMAC "inhibit" command. |
| 0: | A Q = 1 response is generated in recognition of an F(0) or F(2) Read function, or an F(8) function if LAM is set for a valid "N" and "A", but there will be no response (Q = 0) under any other condition. The Q response for empty modules is suppressed (see Q and LAM suppression). |
| X: | An X = 1 (Command Accepted) response is generated when a valid F, N, and A command is generated. |
| L: | Look-At-Me signal is generated from end of digitizing until a module Clear or Clear LAM. LAM is disabled for duration of N, can be permanently enabled or disabled by the Enable or Disable function command, and can be tested by Test LAM. Switch-selectable option causes LAM to be suppressed by empty modules. |
| CAMAC Function Codes: | |
| F(0): | Read registers; requires N and A. A(0) through A(7) are used for channel address. |
| F(2): | Read registers and clear module; requires N, A, and S2. Clears on A(7) only. |
| F(8): | Test Look-At-Me; requires LAM, N and any A from A(0) to A(7). Q is Generated if LAM is present and enabled. |
| F(9): | Clear module (and LAM); requires N and any A from A(0) to A(7), and S2. |
| F(10): | Clear Look-At-Me; requires N, S2 and any A from A(0) to A(7). |
| F(24): | Disable Look-At-Me; requires N, S2 and any A from A(0) to A(7). |
| F(25): | Test module; requires N, S2 and any A from A(0) to A(7). |
| F(26): | Enable Look-At-Me; requires N, S2 and any A from A(0) to A(7). Remains enabled until Z or F(24) applied. |
| Caution: The state of the LAM mask will be arbitrary after power turn-on. | |
| Q and LAM Suppression: | A module receiving no stop inputs will produce no Q response or LAM and appears during readout as an empty CAMAC slot, thus reducing readout time. A Command Accepted response is still generated. The Q and LAM suppress features can be disabled with side-panel switches. |
| Packaging: | In conformance with CAMAC standard for nuclear modules. (ESONE Report EUR4100 or IEEE Report #583). RF-shielded CAMAC #1 module. |
| Power Requirements: | + 24 V at 25 mA
-24 V at 140 mA + 6 V at 600 mA -6 V at 600 mA. |