2132 Operation and Programming Manual





SUMMARY OF CAMAC FUNCTIONS


F(0)o(A(0)+A(1))oN       Read LAM Register (R1=L1, R2=L2)
F(2)o(A(0)+A(1))oN       Read and advance input buffer (data valid if Q=1)
F(9)oA(0)oN              Clear buffers, L1 and L2
F(16)oN                  Write into output buffer (Q=1 if word is accepted at
                         output buffer. Data transfer will then proceed to the
                         HV4032)
F(27)o(AO)oN             Test L1
F(27)o(Al)oN             Test L2
F(10)oA(0)oN             Clear L1
F(10)oA(1)oN             Clear L2
F(26)oA(1)oN             Enable L1
F(26)oA(1)oN             Enable L2
F(24)oA(0)oN             Disable L1
F(24)oA(1)oN             Disable L2
ZoS2                     Clear L1, clear L2, clear buffers, enable L1, disable L2
CoS2                     Clear L1, clear L2, clear buffers





2132 CAMAC INTERFACE

Introduction

The LeCroy Model 2132 is a single-width CAMAC module used to allow bi-directional communication between the CAMAC Dataway and up to 15 HV4032 chassis. Any combination of the HV4032 series mainframe may be used in the daisy chain. The system employs a 5 pair 20 mA current loop serial bus. Data are transmitted at 2400 BAUD using a modified ASCII code. Sixteen bit data words are transmitted as three bytes, each with its own parity bit. Checks for data transmission errors (parity) are accommodated by firmware at the addressed HV4032 chassis or by hardware at the 2132.

The bus consists of two serial data pairs, two bus priority pairs and one pair to differentiate between CAMAC and TTY operation. A cable of up to 1000 feet may be reliably employed between the 2132 and the first HV4032 chassis. Up to 100 feet between chassis may also be employed.

Using the 2132, all front panel operations can be performed remotely (high voltage hardware limit and HV gate are excluded). Commands are available to turn on, turn off, set and read the voltage of any one channel or all channels in any one HV4032 mainframe.

Because CAMAC is so much faster than the serial bus, 40 word memories are employed to buffer both the R and W lines. This allows the user to initiate a read only after all data are transferred, thus minimizing the dead time of the attendant computer. Completion of a routine data transfer to the 2132 sets a low priority LAM (L2). Error signaling uses a high priority LAM (Ll). These LAM's may be detected by CAMAC Look-At-Me and identified through the CAMAC Read (Rl = Ll, R2 = L2). A front panel LAM DISABLE input inhibits L2. This eliminates computer overhead for routine HY maintenance at critical times. A front panel ERROR output is clamped to ground (open collector 300 mA sink) when any mainframe reports an error via the serial bus allowing the user to trigger an external alarm.

The response time of the HV4032 depends upon the specific command issued. "Read One Voltage" commands require only a few msec in contrast with "Turn HV On", which requires approximately 20 seconds. For this reason, a Finished Response is returned after the HV4032 has accomplished the task. Although this response can be disabled, it is strongly recommended that this feature be used.

Communications between the CAMAC 2132 and the HV4032 are of several types. All communication from the 2132 to the HV4032 are of several types. All communication from the 2132 to the HV4032 will be called COMMANDS, and all communication from the HV4032 to the 2132 will be called RESPONSES. The HV4032 will spontaneously respond to indicate a failed channel. Otherwise, the HV4032 will respond only after receipt of a COMMAND from the 2132.

Conversely, most valid COMMANDS from the 2132 will be acknowledged by a RESPONSE from the addressed mainframe. Those commands having a defined response are called HANDSHAKE COMMANDS. These are outlined in Figure 6.10. Any non-handshake command can generate a Finished response (user's option) for convenience of operation.

Front Panel Description

Two LEMO type connectors are provided on the front panel of Model 2132. DISABLE is an external inhibit of the low priority LAM (L2). This eliminates computer overhead for routine HV maintenance at critical times.

ERROR is an open collector 300 mA clamp to ground when a failure is detected at an HV4032. It is intended for use with an external alarm. Maximum Vcc is 30 volts.

The Serial I/0 connector is an Amp Model 201298-1. It is compatable with the HVDC-14 (AMP 201297-1).

CAMAC Operation

The Model 2132 is a dual port device, communication with the HV4032 serial daisy chain via a Universal Asynchronous Receiver Transmitter (UART) and with CAMAC via Dataway. Data words written into the 2132 from CAMAC are loaded into a 40-word deep FIFO and are available for CAMAC readout. Full buffering of both ports has been provided to allow efficient operation in spite of the drastic difference between the speed of the serial daisy chain and that of the computer.

Two levels of interrupt are employed by the 2132 system: High Priority (L1) and Low Priority (L2) LAM's. The Low Priority LAM is used to indicate completion of data transmission from the HV4032 to the 2132 Interface. The L2 may be defeated by a TTY clamp-to-ground at the front panel DISABLE Input. In this way, routine responses from the HV4032's may be masked of when a LAM would be inconvenient. For example, voltages may be measured during data taking and read out, when the computer is inactive.

Data transmission of the Serial Daisy Chain is done at 2400 BAUD using a modified ASCII code. Sixteen-Bit command words written into FIFO 2 are broken into three 6-Bit characters. The UART adds one start bit, two stop bits, and a parity bit. The 2132 control circuitry adds a flag Bit allowing the system to perform framing cheeks. L1 and L2 are used for setting the LAM status on (but not for resetting it).

Eighteen databits are transferred, two of which are used as LAM Status Bits only on transmission to the 2132. Data transfer from the 2132 to the HV4032 Modules is considerably slower than the corresponding response communication. Because of the computer error checking (parity, framing, etc.) the HV4032 requires approximately 100 msec between characters, making the total transfer time approximately 250 msec/word. This timing is controlled by hardware within the 2132. Responses are transmitted at the rate of 15 msec/word. THUS, TRANSMISSION OF 32 VOLTAGE SETTINGS REQUIRES APPROXIMATELY SIX (6) SECONDS. In contrast, reading back 32 voltages can be accommodated in 500 msec.

2132 Programming

Programming of the HV4032/2132 system involves a 16-Bit word format. The constituent syllables that comprise the datawords are as follows:

   M    Mainframe address, M=O used for addressing all units on the daisy chain
        (6-Bits)

   C    Channel number (6-Bits)

   V    Voltage (12-Bits)

   T    Control Tag. See Figure 6.10 (4-Bits)

   S    Software Switch (1-Bit right justified in a 6-Bit field)

The COMMANDS and RESPONSES are indicated in Figure 6.10. These words are written into the 2132 via CAMAC F(16) commands. A list of CAMAC function codes is given at the end of this Section.

Registers which have front panel designations greater than 31 may be written into through CAMAC as follows:

     CAMAC Channel Number     Front Panel Number
           32                          33
           33                          43
           34                          47
           35                          70
           36                          70c
           37                          99

The user software should keep track of values entered into these registers since there are no CAMAC commands to read them. Proper entry of information into these registers may be checked through the front panel.

CAMAC clear (C or Z) is recommended after power up of the 2132. After this initialization it should not be necessary to clear the module again. (Use of clear function may, in fact, cause erroneous data to be read out should it coincide with data transferred from an HV4032).

Data buffer (FIFO) clearing can be performed by generating read cycles, F(2), until Q response equals zero. During normal read, F(2) should be continued until Q=O to ensure all data available has been cleared.

A Q response following a write command, F(16), indicates that the 16 bit word had been accepted by the 2132. It will be transferred thereafter according to the timing set internally by hardware in the 2132 Interface.

The Finished Response can be used for non-handshake commands to inform the user when the command is completed. In the given example, the 33 words used to modify the voltage of 32 channels in mainframe 16 will be transmitted to the HV4032 at a rate determined by hardware in the 2132 Interface. The HV4032 will process this data, look for errors (parity), and send a Finished response on completion of the command. If the high voltage is ON the response will occur after the voltages have been modified. If the high voltage is OFF the response will be given upon receipt of the data.

After the high voltage ON command is used, a delay of approximately 20 seconds allowing voltage run-up will be experienced before the finished response will be given. (Response is generated when the microprocessor is no longer "busy"). The user should modify his software for his convenience so that considerable computing time is not lost in waiting for this response.

In generating commands to the HV4032 via the 2132 CAMAC Interface, care should be exercised in writing into the FIFO 2. Though the buffer is 40 words deep it must be realized that the buffer data is transferred to the HV4032 at a much slower rate than the CAMAC dataway can write. Do not attempt to write more than 40 words at one time.

If several commands are to be given, i.e., modify 32 channels for more than one mainframe, wait for a response from the first mainframe before addressing the next.

A module zero address can be used to address all mainframes in a daisy chain. Never use this command where a response totaling more than 40 words will occur. For example, requesting 32 ADC voltages from all mainframes.

Error detection is performed by decoding the 16-Bit response words. The lower order four bits will define the nature of the error. (i.e., 12 parity, 13 = overwrite). A parity error implies a command to a HV4032 which was not recognized. This can be generated by any unit in a daisy chain as all units will see the command from the 2132, but only the HV4032 recognizing the address should respond to the command given.

Each of the three characters in a word has a parity bit which is checked before the data is processed. If a parity error is detected, the command will be aborted and the user will have to re-initiate the command.

An overwrite error will occur should a second character arrive before the first character is processed. The likelihood of this occurring is very small since the timing is controlled by hardware in the 2132 Interface. In the event that an overwrite error is detected, the command will be aborted and will necessitate re-initialization of the command as above. Both overwrite and parity are errors detected at the HV4032.

Transmission error is detected at the 2132 and includes either parity or overwrite error of a response.