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Global Set/Reset (GSR)

“”“All Xilinx FPGA devices have a dedicated asynchronous reset called Global Set/Reset (GSR). GSR is automatically asserted at the end of FPGA configuration, regardless of the design. For gate-level simulation, this GSR signal is also inserted to mimic this operation to allow accurate simulation of the initialized design as it happens in the silicon. Adding another asynchronous reset to the actual code only duplicates this dedicated feature. It is not necessary for device initialization or simulation initialization.”“” []

Relationally placed macros

use RLOC instead of LOC constraint

Example: FIXME

xilinx/start.txt · Last modified: 2013/09/26 21:16 by sky