Typically partial reconfiguration is done through the Internal Configuration Access Port (ICAP). IIRC this provides a frame based interface very similar to that used in JTAG.
One of the more common applications or PR is to create partition blocks and do partial updates on FPGAs. Traditionally this has been only possible on the block based Virtex devices because the spartan (up to 3?) were column based which meant that a related function was spread out too much. There are a few third party solutions that do PR on Xilinx FPGAs, I believe Xilinx bought one of them
Another application is the Soft Error Migration (SEM) core which uses PR internally to do the correction. More details: http://www.xilinx.com/support/documentation/ip_documentation/sem/v3_4/pg036_sem.pdf
Shift Register LUTs (SRL) can be used to reconfigure a LUT at runtime. They are more limited than full frame reconfiguration but are better documented, easier to use, and finer grained. See http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf