Tutorial (UG676 (v14.1) May 8, 2012): http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/PlanAhead_Tutorial_Design_Analysis_Floorplan.pdf

Windows 8

person: planahead is broken on Windows 8.x because of SmartHeap and there's no straightforward workaround
person: http://escapehatchlabs.com/blog/fixing-64-bit-xilinx-apps-crashing-windows-8-1/ for what SmartHeap does
...
person: there's a better way to fix the issue:
person: replace the smartheap DLLs that come with ISE with those that come with the latest Vivado

Viewing PAR results

Its a little non-intuitive how to view from command line

Prereq files:

  • .ngc (xst)
  • .ncd (par)
  • .twx (timingan)

Do:

  1. Go to your build dir with .ngc, .ngd, etc
  2. Launch planAhead
  3. Create New Project GUI pops up
  4. Hit Next
  5. Project name, etc: defaults are fine
  6. Hit Next
  7. Keep default (Import ISE place & Route Results)
  8. Hit Next
  9. Netlist sources: add your .ngc(s)
    • If you forget to do this it will churn for a while and then nothing will show up
    • Don't forget to add IP cores
  10. Hit Next
  11. Add constraints: do nothing
  12. Hit Next
  13. Part: select your part
    • Use the search function to quickly find your part
  14. Import ISE Impleentation Results: give .ncd and .twx
  15. Hit Next
  16. Select the top module
  17. Let it churn for a bit (3 minutes)
  18. Open implemented design
  19. Hit OK
  20. Let it churn for a bit (1 minute)
  21. Ifd you get something like this: While importing this netlist, 11 undefined instances were found and converted to black boxes
    • You forgot to add some IP cores
    • Ctrl-F to find black boxes
    • Fix by doing File ⇒ add sources ⇒ Add design sources ⇒ Add files
    • Hmm this didn't actually fix it. I guess you have to re-run
    • File ⇒ new synthesized design?

If everything succeeds you should get something like this:

The green lines are IO nets. They can be toggled on/off with a button at the left

_FCKG_BLANK_TD_

Navigating

Unfortunately finding a specific component isn't very intuitive. To do this:

  • Use find or the heirarchy to search for something
  • You have it selected but where is it? (sometimes obvious, sometimes not)
  • Turn off “Show Instance Connections” on the left side
  • Upper right command command box: Pan Selection
  • View should be centered on it. Zoom in further if you still don't see it.

To find a pin (ex: AP26):

  • Find site
  • Enter it

Secure IP

CRITICAL WARNING: [EDIF 20-94] Could not read core file for 'my_shitty_core' defined in file 'my_shitty_project.ngc' because ngc2edif command failed with the following message:
ERROR:NetListWriters - The design contains secured core(s). Creation of the
   output netlist is prohibited. A license for the secure IP is required from
   Xilinx.

Not sure what to do about this. It sounds like the IP core I bought from vendor used some Xilinx licensed IP that Xilinx is complaining about

EDIF

Seems to run ngc2edif on everything. May be able to acelerate runs by pre-converting everything to EDIF

References

 
xilinx/planahead.txt · Last modified: 2015/07/16 20:41 by mcmaster-guest
 
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