ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc [UCF constraint file] -p [device name] [input NGC file] [output NGD file]
ERROR:NgdBuild:455 - logical net 'core1/Mcompar_ddrf_rd_data_count_est_max_50_ddrf_rd_data_count_est_50[ 31]_LessThan_10_o_lutdi14' has multiple driver(s): pin G on block XST_GND with type GND, pin PAD on block core1/Mcompar_ddrf_rd_data_count_est_max_50_ddrf_rd_data_count_est_50[3 1]_LessThan_10_o_lutdi14 with type PAD, pin Q on block core2/dma0_rd_fifo_big0.i_async_fifo_sata_to_dma_rd0/U0/xst_fi fo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwf t_i with type FDP
TLDR: wire assigned to wire [3:0]. Added 0's and connected to pads which blew things up
This took me a half day to troubleshoot and was ultimately fixed by doing two things:
The first I can't help you with, it depends on your design too much the best way to go about that.
The second was tricky. It only works from the ISE GUI but this can be fixed relatively easily by using PlanAhead (method I used) or creating a blank project with the .ngc. However, the ISE RTL viewer tool only works on PAR'd designs and not on just netlists. Since my design was failing ngdbuild, let alone PAR, this was a no-go.