The Xilinx CORE Generator System (“coregen”) is used to generate “IP Cores”, a collection of generated HDL and/or netlist files to accompolish a specific task. For example, the Memory Interface Generator (MIG) is used to create an easy to use performant interface to DDR without having to know too much about the intimate details about how DDR works. In ISE it can be launched as a standalone tool or from within ISE. In Vivado the wizards can be run but not the coregen UI. I do not know how to upgrade cores in Vivado.
An IP core is grayed out if the IP core part number doesn't match the project part number
Sometimes you need to fork an IP core as the system matures. Its not too hard, but non-obvious as I don't think the GUI provides any method to do so
Create a coregen project *in its own directory*. Coregen spits out lots of files and they will be difficult to manage if you don't put them in their own direcotry.
Page through the IP catalog and find a core you want to generate. Then right click on it and start the wizard.
If you are running a different version of coregen than the core was originally generated with, read the upgrade section first. Anyway, if you right click to regenerate your eyes may glaze over at the 8 or so very similar sounding options that pop up. They are something like…
TLDR: for most users both options will do the same thing
Details: the coregen project has a part number associated with it to use when creating new IP. However, each generated core also has a part number associated with it. If you upgrade your project the two might get out of sync. For example, if you upgrade the project from Spartan 6 to Kintex 7 the IP is *not* automatically upgraded. If you say to generate with original settings it will generate it for the Spartan 6 despite that its now a Kintex 7 project. if you say to gnerate with current settings it will change the IP to Kintex 7 before generating. If your version of coregen does not support a select part number you may have one or both options missing
Cores can have the following upgrade statuses:
Sometimes for one reason or another an IP core can't be upgraded. For exmaple, I wasn't able to upgrade from MIG 1.7 to 1.9 despite them being pretty close. Don't fret though, the manul upgrade process isn't too bad if you are a little careful.
I use a combination of the two strategies:
As far as I can tell there is no way to delete cores from the UI. The project files are auto generated, don't try to edit them. Instead do the folloing:
The core should now be gone from the list
Defines an individual IP core: “This file contains the customisation parameters for a Xilinx CORE Generator IP GUI.”
Coregen project file
Source file: yes
# Date: Fri Aug 10 20:20:03 2013 SET addpads = false SET asysymbol = true SET busformat = BusFormatAngleBracketNotRipped ...
Copy of the console log
Source file: no
Welcome to Xilinx CORE Generator. Help system initialized. The IP Catalog has been reloaded. Opening project file /home/.../coregen.cgp. ...
XML file with various core options used in the project. Completely regenerated when project.cgp is opened
Source file: no
<?xml version="1.0" encoding="UTF-8"?> <spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" > <spirit:vendor>xilinx.com</spirit:vendor> <spirit:library>project</spirit:library> <spirit:name>coregen</spirit:name> <spirit:version>1.0</spirit:version> <spirit:componentInstances> <spirit:componentInstance> <spirit:instanceName>my_fifo</spirit:instanceName> <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3" /> <spirit:configurableElementValues> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">my_fifo</spirit:configurableElementValue> ...
SETPROJECT "C:/.../coregen.cgp" LAUNCHXCO "C:/.../DDR3_Controller.xco"
Source file: probbaly not