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xilinx:xst [2015/07/20 22:35]
mcmaster-guest
xilinx:xst [2015/07/20 22:35] (current)
mcmaster-guest
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 </​code>​ </​code>​
  
 +One idea might be to export your IP cores as VHDL even if you have a Verilog audience since it handles this better.
  
-One idea might be to export your IP cores as VHDL even if you have a Verilog audience since it handles this better.  ​But if you are a Verilog purist there is a way to eliminate the above warning using something like: +But if you are a Verilog purist there is a way to eliminate the above warning using something like:
  
 <​code>​ <​code>​
 
xilinx/xst.txt · Last modified: 2015/07/20 22:35 by mcmaster-guest
 
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