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xilinx:xst [2015/07/20 22:35]
mcmaster-guest [Black boxes]
xilinx:xst [2015/07/20 22:35]
mcmaster-guest
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 endmodule endmodule
 </​code>​ </​code>​
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 </​code>​ </​code>​
  
 +One idea might be to export your IP cores as VHDL even if you have a Verilog audience since it handles this better.
  
-_FCKG_BLANK_TD_ +But if you are a Verilog purist there is a way to eliminate the above warning using something like:
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-One idea might be to export your IP cores as VHDL even if you have a Verilog audience since it handles this better.  ​But if you are a Verilog purist there is a way to eliminate the above warning using something like: +
  
 <​code>​ <​code>​
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 secret_sauce saucy(.i1(stuff1),​ .i2(stuff2),​ .o(output));​ secret_sauce saucy(.i1(stuff1),​ .i2(stuff2),​ .o(output));​
 </​code>​ </​code>​
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 Unfortunately you have to put this on every instantiation. ​ If you had to do this a lot you could put a wrapper on secret_sauce. ​ See XST User Guide "​BoxType (BOX_TYPE)"​ for more detail. Unfortunately you have to put this on every instantiation. ​ If you had to do this a lot you could put a wrapper on secret_sauce. ​ See XST User Guide "​BoxType (BOX_TYPE)"​ for more detail.
  
 
xilinx/xst.txt · Last modified: 2015/07/20 22:35 by mcmaster-guest
 
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