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xilinx:ngdbuild [2015/04/10 17:06]
mcmaster-guest [ERROR: logic net has multiple driver(s)]
xilinx:ngdbuild [2015/04/16 23:18] (current)
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    t_i with type FDP    t_i with type FDP
 </​code>​ </​code>​
 Related: http://​www.xilinx.com/​support/​answers/​32847.html Related: http://​www.xilinx.com/​support/​answers/​32847.html
 +TLDR: wire assigned to wire [3:​0]. ​ Added 0's and connected to pads which blew things up
 +This took me a half day to troubleshoot and was ultimately fixed by doing two things:
 +  * Cutting the design down to smaller pieces where possible
 +  * Opening design in RTL viewer
 +The first I can't help you with, it depends on your design too much the best way to go about that.
 +The second was tricky. ​ It only works from the ISE GUI but this can be fixed relatively easily by using PlanAhead (method I used) or creating a blank project with the .ngc.  However, the ISE RTL viewer tool only works on PAR'd designs and not on just netlists. ​ Since my design was failing ngdbuild, let alone PAR, this was a no-go.
xilinx/ngdbuild.txt ยท Last modified: 2015/04/16 23:18 by mcmaster-guest
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