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xilinx:netgen [2013/01/22 00:42] (current)
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 +Generates a fully synthesized VHDL or Verilog netlist (raw slice primitives connected by wires) from a [[NGC]] file. Useful for simulation, static timing, etc.
 
xilinx/netgen.txt ยท Last modified: 2013/01/22 00:42 (external edit)
 
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