Issues

Introspection

ISE iSim 14.5 Crashes when I try to peer into modules. For example:

wire [3:0] command_fsm_value = command_layer.command_fsm_value;

Workaround: route signals out of ports and then assign it

wire [3:0] command_fsm_value;
...
my_module my_module(
...
    .command_fsm_value_out(command_fsm_value));

Post place and route simulation

I believe all this does is generate .v file(s) that have delays put into them. In theory, this allows you to plop it directly into your favorite simulator without any magic. Although simple in theory, I've had several issues getting this to work correctly

I've asked several people why you'd want to do this. I haven't gotten very good answers, most of them involve work arounds for hacks. For example:

  • Debugging timing ignore issues (think: should you have the TIG in the first place?)
  • Under-constrained design

IIRC this does not do any PVT checking. In fact, I don't believe that Xilnx guarantees PVT safe output either. Not sure how you are supposed to actually meet PVT if its important in your application

something like "previous step did complete"

this was due to bad depdnency checks in ISE. I fiddled re-running it a few different ways and it eventually worked

Can not find design unit work.glbl

ERROR:Simulator:702 - Can not find design unit work.glbl in library work located at isim/work 

as yet unsolved….

Maybe help: http://vhdlguru.blogspot.com/2010/03/xilinx-error-simulator702-can-not-find.html

Value for parameter unknown is not constant

If you get:

Value for parameter unknown is not constant

Example:

ClkGen #(CLK_WIDTH(123), CLK_TARG(456), ODD_DIV(0)) my_clkgen (nrst,clk1,clk2);

You are missing the .'s:

ClkGen #(.CLK_WIDTH(123), .CLK_TARG(456), .ODD_DIV(0)) my_clkgen (nrst,clk1,clk2);

Maybe related: http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/

Zero delay oscillation

Example message:

ERROR: at 0 ps: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File "..._tb.v" Line 23.
Please correct this code in order to advance past the current simulation time.

Cause:

I've typically found this to be caused by a construct like this:

parameter CLK_PERIOD = 1;
initial begin
    clk <= 1'b1;
    forever begin
        #(CLK_PERIOD/2);
        clk <= ~clk;
    end
end

Which is usually fine. However, if CLK_PERIOD is defined as “1” then 1 / 2 = 0 and it runs infinitely fast ⇒ never settle ⇒ timeout

Solution:

Define CLOCK_PERIOD as a float:

parameter CLK_PERIOD = 1.0;

So that 1.0 / 2 = 0.5. You could of course alternatively do:

#(CLK_PERIOD/2.0);

Exceptional condition

Example:

ERROR: In process my_module.vCont_56_1
 FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. 
 Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to 
 http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. 
 For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
INFO: Simulator is stopped.

Where 56 is the file line number.

Cause:

In my case it was caused by something like this:

module my_moudle(
        input wire a,
        input wire b,
        output reg c);
    assign c = a && b;
    always @(*) begin
        c = 1'b0;
    end
endmodule

That is, c had been assigned both globally and by a process.

 
xilinx/isim.txt · Last modified: 2016/01/21 16:14 by mcmaster-guest
 
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