The Xilinx CORE Generator System (“coregen”) is used to generate “IP Cores”, a collection of generated HDL and/or netlist files to accompolish a specific task. For example, the Memory Interface Generator (MIG) is used to create an easy to use performant interface to DDR without having to know too much about the intimate details about how DDR works. In ISE it can be launched as a standalone tool or from within ISE. In Vivado the wizards can be run but not the coregen UI. I do not know how to upgrade cores in Vivado.

An IP core is grayed out if the IP core part number doesn't match the project part number

List of IP cores

Copying a core

Sometimes you need to fork an IP core as the system matures. Its not too hard, but non-obvious as I don't think the GUI provides any method to do so


  1. Close the coregen project
  2. Copy old_core.xco to new_core.xco
  3. Edit newcore.xco
    • Find a line like: CSET component_name=old_core
    • Change it to: CSET component_name=new_core
  4. Open the coregen project. The new core should be there; recustomize and generate as needed

Generating cores

Create a coregen project *in its own directory*. Coregen spits out lots of files and they will be difficult to manage if you don't put them in their own direcotry.

Page through the IP catalog and find a core you want to generate. Then right click on it and start the wizard.

Re-generating cores

If you are running a different version of coregen than the core was originally generated with, read the upgrade section first. Anyway, if you right click to regenerate your eyes may glaze over at the 8 or so very similar sounding options that pop up. They are something like…

"current project settings" vs "original project settings"

TLDR: for most users both options will do the same thing

Details: the coregen project has a part number associated with it to use when creating new IP. However, each generated core also has a part number associated with it. If you upgrade your project the two might get out of sync. For example, if you upgrade the project from Spartan 6 to Kintex 7 the IP is *not* automatically upgraded. If you say to generate with original settings it will generate it for the Spartan 6 despite that its now a Kintex 7 project. if you say to gnerate with current settings it will change the IP to Kintex 7 before generating. If your version of coregen does not support a select part number you may have one or both options missing

Upgrading cores

Cores can have the following upgrade statuses:

  • Production: don't do anything, your core is already at a fully supported version
  • Pre-production: the core likely has one issue or another that means you should be careful using it. Sometimes you can upgade to a newer version of ISE and get a production grade core
  • Upgradable: cannot generate original version but there is a newer version of the core availible
  • Superseeded: can still generate original version but a newer (stable?) version is availible
  • Blank: the worst status. Not only can you not upgrade it or regenerate the old version, but there is no suggested upgrade path. This doesn't necessarily mean that there isn't an obvious upgrade path though. See if there is a close matching core and follow the “Manual upgrade” section

Manual upgrade

Sometimes for one reason or another an IP core can't be upgraded. For exmaple, I wasn't able to upgrade from MIG 1.7 to 1.9 despite them being pretty close. Don't fret though, the manul upgrade process isn't too bad if you are a little careful.

I use a combination of the two strategies:

  • If you are still able to re-generate the old core (on current system or another), create a new IP core and run the re-customize wizard on the old core at the same time. Go through the wizards step by step and compare options. Some screens may re-arrange but it should let you get through the bulk of the options pretty quickly. Rule of thumb: if you are unsure about a new option keep the default setting. Of course, I highly advise you look into anything you don't understand!
  • Scrape the coregen.cgc file for the old core settings and match them up to the new GUI options. This works well 90% of the time but sometimes can be difficult to correlate

Deleting cores

As far as I can tell there is no way to delete cores from the UI. The project files are auto generated, don't try to edit them. Instead do the folloing:

  1. Close the coregen project
  2. Delete all of the files related to the core in your corgen directory (ex: rm -rf mig_blah_*)
    • Ultimately deleting the .xco is what makes it disappear from the GUI
  3. Open the coregen project

The core should now be gone from the list



Defines an individual IP core: “This file contains the customisation parameters for a Xilinx CORE Generator IP GUI.”


  • #: comment
    • Ex: # Xilinx Core Generator version 14.5
    • Ex: # CRC: bce1ba2e
  • SET: ?
    • Ex: SET addpads = false
  • CSET: ?
    • Ex: CSET add_ngc_constraint_axi=false
  • SELECT: ?
    • Ex: SELECT FIFO_Generator
  • MISC: ?
    • Ex: MISC pkg_timestamp=2012-11-19T12:39:56Z
    • Ex: GENERATE


Coregen project file

Source file: yes


# Date: Fri Aug 10 20:20:03 2013

SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped


Copy of the console log

Source file: no


Welcome to Xilinx CORE Generator.
Help system initialized.
The IP Catalog has been reloaded.
Opening project file


XML file with various core options used in the project. Completely regenerated when project.cgp is opened

Source file: no


<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="" xmlns:xsi="" xmlns:xilinx="" >
         <spirit:componentRef spirit:vendor="" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3" />
            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">my_fifo</spirit:configurableElementValue>



SETPROJECT "C:/.../coregen.cgp"
LAUNCHXCO "C:/.../DDR3_Controller.xco"

Source file: probbaly not

xilinx/coregen.txt · Last modified: 2014/02/10 20:37 by sky
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