Clocks out to GPIO

Goal: needed to output a GTX phase locked clock to create eye diagram

Problem: due to fabric limitations, clocks cannot always be directly placed from, say, global routing to an IOB

There are a few tricks around this. This seems to be the most widely suggested:

//Clocks cannot be directly routed to IOB
//Instead, instantiate an ODDR buffer with data that follows clock signal
  .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
  .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
) ODDR_inst (
  .Q(xo_mgtrefclk0),   // 1-bit DDR output
  .C(clk_gtx_unbuf_tig),   // 1-bit clock input
  .CE('b1), // 1-bit clock enable input
  .D1('b1), // 1-bit data input (positive edge)
  .D2('b0), // 1-bit data input (negative edge)
  .R('b0),   // 1-bit reset
  .S('b0)    // 1-bit set

However, I found this was giving me issues sometimes. I just needed an in phase clock and so while this divides by two was working:

reg clk_gtx_unbuf_tig_r;
always @(posedge clk_gtx_buf) begin
    clk_gtx_unbuf_tig_r <= ~clk_gtx_unbuf_tig_r;
assign xo_mgtrefclk0 = clk_gtx_unbuf_tig_r;

Sometimes I needed a BUFG in between. One way or hte other I was able to hack around it to solve for now, but needs more looking into…

Some code that was working fine for a while broke after I deleted some stuff. Got this message:

ERROR:PhysDesignRules:2476 - Unsupported clocking structure. The IBUFDS_GTXE1
   block <gtx_refclk_ibufds_i> is driving a BUFG block <clk_gtx_unbuf_tig_BUFG>
   which drives the MGTREFCLKRX0 pin of a GTXE1 block
   <sata_phy/sata_gtx_dual_i/gtx0_sata_i/gtxe1_i>, which is not a valid

However, the .v pretty clearly does not do this. In fact, it very clearly has a KEEP constraint that was supposed to prevent any madness like this. It does have a BUFG but the signal in question was branched before it was used. Not sure if this somehow caused a BUFG to be inferred.


Process Monitor Vehicle (PMV)

Hi All,

as I had guessed for long time the PMV primitive is actually the
on-chip oscillator, most likely it is the same oscillator that is used
for configuration. And it can be used from user designs as well. PMV is
present in all recent FPGAs.

When I opened webcase about the issue that Xilinx tools made fatal
failure when I tried to use the PMV from an hard macro the response was
that, "you dont need to know" - well now I know :)

Using Xilinx PMV primitive 	PDF		Print		E-mail	
Written by Administrator   
Wednesday, 30 August 2006
PMV is Xilinx on-chip oscillator that is usually not accessible
for user designs. PMV primitive can actually be used, with 
some care: for Virtex-4 at least all DCM in the FPGA must be 
connected in the way that they are not optimized away. If that
is not the case then Xilinx tools try to put the unused DCM into 
autocalibrate mode that utilizes the PMV, and as there is only 
one PMV there will be error at mapping.

The PMV as instantiated below delivers about 40MHz clock in 
Virtex-4FX, tested with real devices.

component PMV port ( 
      EN : in std_ulogic;
      A0 : in std_ulogic;      
      A1 : in std_ulogic;      
      A2 : in std_ulogic;      
      A3 : in std_ulogic;      
      A4 : in std_ulogic;      
      A5 : in std_ulogic;      
      ODIV2 : out std_logic;
      ODIV4 : out std_logic;
      O : out std_ulogic);
end component;
	my_pmv: PMV port map (   
		EN => '0',        
		A0 => '0',
		A1 => '0',
		A2 => '1',
		A3 => '0',
		A4 => '0',
		A5 => '0',
		O => O,
		ODIV2 => open,
		ODIV4 => open

Last Updated ( Wednesday, 30 August 2006 )
Xilinx hasnt provided yet any examples with MicroBlaze on Spartan-3A Starterkit, so we have prepared one for you. 
xilinx/clocking.txt · Last modified: 2015/07/17 13:02 by mcmaster-guest
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