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xilinx:chipscope [2016/01/11 21:27]
mcmaster-guest
xilinx:chipscope [2016/01/11 21:33] (current)
mcmaster-guest
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 The IP core I had was created with an earlier version of ICON/ILA (forget what). ​ I upgraded to ICON 1.06.a, ILA 1.05.a and things started to work.  One big difference is that this adds JTAG clock ucf TIG where previously there were no constraints...not sure if this can somehow help timing. ​ I was expecting a TNM clock constraint on JTAG. The IP core I had was created with an earlier version of ICON/ILA (forget what). ​ I upgraded to ICON 1.06.a, ILA 1.05.a and things started to work.  One big difference is that this adds JTAG clock ucf TIG where previously there were no constraints...not sure if this can somehow help timing. ​ I was expecting a TNM clock constraint on JTAG.
  
-2016-01-11: 14.5 build w/ 14.3 lab tools did not detect ILA.  Switching JTAG USB port to PC w/ 14.5 made ILA show up+2016-01-11: 14.5 build w/ 14.3 lab tools did not detect ILA.  Switching JTAG USB port to PC w/ 14.5 made ILA show up.  Upgraded original machine to 14.5 and it showed up.
  
 I also saw [[http://​forums.xilinx.com/​t5/​Design-Tools-Others/​Chipscope-10-1-3-quot-Found-0-core-units-in-the-JTAG-device/​td-p/​23725|this]] ("edit : i got it working by reducing the speed of the usb Jtag, it was set to 24MHz initially, and I reduce it to 3MHz") which sounds like the same problem: they had to lower clock speed from GUI, presumably because cores weren'​t constrained right. ​ Looks like my default is 3 MHz I also saw [[http://​forums.xilinx.com/​t5/​Design-Tools-Others/​Chipscope-10-1-3-quot-Found-0-core-units-in-the-JTAG-device/​td-p/​23725|this]] ("edit : i got it working by reducing the speed of the usb Jtag, it was set to 24MHz initially, and I reduce it to 3MHz") which sounds like the same problem: they had to lower clock speed from GUI, presumably because cores weren'​t constrained right. ​ Looks like my default is 3 MHz
 
xilinx/chipscope.txt ยท Last modified: 2016/01/11 21:33 by mcmaster-guest
 
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