10/14/2014 talk

JM listened to presentation on it (from author?). Takeaways:

  • Essentially a SCALA library that provides a lot of synatic sugar and such to make a semi-custom language
  • HDL intermediate representation. IR can generate verilog or C++ simulator code leading to fast simulations
  • Primary market chip designers
    • A number of real world chips fabricated
  • Limited/low use with FPGAs?
  • Instantiating IP painful but possible using wrapper scripts. They are working to improve this
  • 1 full time developer. Commercial support from several entities
  • Focus on making HDL easy over high degree of control
    • Ex: focus on single clock domain designs. Clock is generally hidden from the user
    • Trying to make easy Arduino integration
  • Misc research projects like open CPU written in it
chisel/start.txt · Last modified: 2014/10/14 16:21 by mcmaster-guest
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