[[vendor:yamaha:opl2]]
 
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vendor:yamaha:opl2 [2019/04/07 21:49]
lord_nightmare add link to D0/D1 debug info 		vendor:yamaha:opl2 [2019/12/29 01:57]
nukeykt Fix typo
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 ===== YM2413/VRC7 ======= ===== YM2413/VRC7 =======
 OPL Light/Light, aka OPLL, is a cost-reduced version of OPL2 that hard-codes 15 preset instruments and allows for 1 custom instrument to be created. The instrument ROM saves silicon die space compared to registers. One nagging problem with OPLL is that up until recently, there was no known way to extract the instrument ROM contents. Thus, emulation of preset instruments was based on empirical approximations. OPL Light/Light, aka OPLL, is a cost-reduced version of OPL2 that hard-codes 15 preset instruments and allows for 1 custom instrument to be created. The instrument ROM saves silicon die space compared to registers. One nagging problem with OPLL is that up until recently, there was no known way to extract the instrument ROM contents. Thus, emulation of preset instruments was based on empirical approximations.
-=== YM2413 Instruments === +=== YM2413 D0/D1 debug state === 
-There is at present no die image of YM2413. In the near future, [[https://whitequark.org|whitequark]] will provide a die image suitable for RE. It is anticipated that the instruments ROM will be an implant ROM. This implies a delayering or staining to read out its contents. +from Nuke.YKT's notes at https://pastebin.com/H5s4WQQ8 :
-=== YM2413 TEST register (0x0F) ===+
 <code> <code>
-TEST (0x0F) +YM2413 test data output format(!!not verified on hardware!!). 
- 76543210 +/CS = 0 
- |||||||\- DAC test enable (enables DAC output from the top 4 bits of address 0x10 (0x10 is normally the frequency LSB bits for channel 0) +/WE = 1 
- ||||||\-- ? +A0  = 0 
- |||||\--- ? +D0 and D1 serially output test data with internal clock rate 
- ||||\---- This bit, if set, silences the FM sound output. How exactly is unknown. (On YM2151 this bit freezes the phase counters and lfo counters) +Internal clock rate is MCLK/4 
- |||\----- ? +Clock 0  1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 17 
- ||\------ ? +D0:   P8 P7 P6 P5 P4 P3 P2 P1 P0 E6 E5 E4 E2 E1 E0 0  0  0 
- |\------- ? +D1:   C8 C7 C6 C5 C4 C3 C2 C1 C0 0  0  0  0  0  0  0  0  0 
- \-------- ?+  
 +Px - Operator 0 phase generator output LSB bits 
 +Ex - Operator 17 envelope generator output 
 +Cx - Channel 6(?) output
 </code> </code>
  
-=== YM2413 D0/D1 debug state === 
-see Nuke.YKT's notes at https://pastebin.com/H5s4WQQ8 
  
-=== VRC7 TEST register (0x0F) ===+=== YM2413 and VRC7 TEST register (0x0F) ===
 <code> <code>
 TEST (0x0F) TEST (0x0F)
  76543210  76543210
- |||||||\- if 1, Disables Car/Mod EG units, EG output is forced to 0 (max volume) + |||||||\- if 1, Disables Car/Mod EG units, EG output is forced to 0 (max volume). This can be used as a crude DAC test, see below. 
- ||||||\-- if 1, resets (and holds, while active) the Trem and Vib LFO counts to 0+ ||||||\-- if 1, resets (and holds, while active) the Trem and Vib LFO counts to 0, and resets the rhythm LFSR to all 1s.
  |||||\--- if 1, resets (and holds, while active) the PG count for Car/Mod at 0 (this effectively silences the chip)  |||||\--- if 1, resets (and holds, while active) the PG count for Car/Mod at 0 (this effectively silences the chip)
  ||||\---- if 1, the EG unit clock comes from VRC7 'D2' Pin, and the Trem and Vib LFO clock dividers are disabled, so they increment once per clock (x64 and x1024 their usual clock rates, respectively)  ||||\---- if 1, the EG unit clock comes from VRC7 'D2' Pin, and the Trem and Vib LFO clock dividers are disabled, so they increment once per clock (x64 and x1024 their usual clock rates, respectively)
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 </code> </code>
  
 +If bit 0 is set, this can be combined with setting bit 2, and writing the 'desired DAC' (really, offset in the SINE ROM) value to register 0x10+n (or any of the other frequency registers). Bit 2 will reset the phase generator offset to 0 every tick, which combined with 0x10 to set the frequency LSB (which is added to the phase generator offset), can be used to crudely force the DAC to any specific value in the sine wave. Setting the frequency MSB (0x20+n) should also similarly affect this. The Volume and instrument settings in (0x30+n) still take effect, as do carrier/modulator effects, so keep this in mind.
  
 === VRC7 Debug Mode === === VRC7 Debug Mode ===
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 <nukeykt> For all configs A13(pin 2)=1, M2(pin 47)=0, P15=0, [...] For config 0: /CS=1, /WR=1, A0=1, for config 1: /CS=1, /WR=1, A0=0, etc. <nukeykt> For all configs A13(pin 2)=1, M2(pin 47)=0, P15=0, [...] For config 0: /CS=1, /WR=1, A0=1, for config 1: /CS=1, /WR=1, A0=0, etc.
 +
 +==== YM2413 Instrument ROM ====
 +These values were initially created using hardware tests by nukeykt, but later were corrected by crosschecking data with ym2413b die shot.
 +<code>
 +/* Order of array = { modulator, carrier } */
 +typedef struct {
 +    Bit8u tl;
 +    Bit8u dc;
 +    Bit8u dm;
 +    Bit8u fb;
 +    Bit8u am[2];
 +    Bit8u vib[2];
 +    Bit8u et[2];
 +    Bit8u ksr[2];
 +    Bit8u multi[2];
 +    Bit8u ksl[2];
 +    Bit8u ar[2];
 +    Bit8u dr[2];
 +    Bit8u sl[2];
 +    Bit8u rr[2];
 +} opll_patch_t;
 +
 +static const opll_patch_t patch_ym2413[opll_patch_max] = {
 +    { 0x1e, 0x01, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x07 },{ 0x00, 0x08 },{ 0x00, 0x01 },{ 0x00, 0x07 } },
 +    { 0x1a, 0x00, 0x01, 0x05,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x0f },{ 0x08, 0x07 },{ 0x02, 0x01 },{ 0x03, 0x03 } },
 +    { 0x19, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0c },{ 0x02, 0x04 },{ 0x01, 0x02 },{ 0x01, 0x03 } },
 +    { 0x0e, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x07, 0x02 },{ 0x00, 0x07 } },
 +    { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x06 },{ 0x00, 0x02 },{ 0x00, 0x08 } },
 +    { 0x16, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x02 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x08 } },
 +    { 0x1d, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x07 } },
 +    { 0x2d, 0x01, 0x00, 0x04,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x07 },{ 0x02, 0x02 },{ 0x00, 0x00 },{ 0x00, 0x07 } },
 +    { 0x1b, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x06, 0x06 },{ 0x04, 0x05 },{ 0x01, 0x01 },{ 0x00, 0x07 } },
 +    { 0x0b, 0x01, 0x01, 0x00,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x0f },{ 0x05, 0x07 },{ 0x07, 0x00 },{ 0x01, 0x07 } },
 +    { 0x03, 0x01, 0x00, 0x01,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x0a, 0x04 },{ 0x01, 0x00 },{ 0x00, 0x04 } },
 +    { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x02, 0x02 } },
 +    { 0x0c, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x0f },{ 0x02, 0x05 },{ 0x02, 0x04 },{ 0x00, 0x02 } },
 +    { 0x15, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x0c, 0x09 },{ 0x09, 0x05 },{ 0x00, 0x00 },{ 0x03, 0x02 } },
 +    { 0x09, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x01, 0x04 },{ 0x04, 0x01 },{ 0x00, 0x03 } },
 +
 +    { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
 +    { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
 +    { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
 +    { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
 +    { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x04 },{ 0x00, 0x08 } },
 +    { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
 +};
 +</code>
 +
 +This translates into a patchset of:
 +<code>
 +0: user patch (irrelevant)
 +1: $71 $61 $1E $17 $D0 $78 $00 $17
 +2: $13 $41 $1A $0D $D8 $F7 $23 $13
 +3: $13 $01 $99 $00 $F2 $C4 $11 $23
 +4: $31 $61 $0E $07 $A8 $64 $70 $27
 +5: $32 $21 $1E $06 $E0 $76 $00 $28
 +6: $31 $22 $16 $05 $E0 $71 $00 $18
 +7: $21 $61 $1D $07 $82 $81 $10 $07
 +8: $23 $21 $2D $14 $A2 $72 $00 $07
 +9: $61 $61 $1B $06 $64 $65 $10 $17
 +A: $41 $61 $0B $18 $85 $F7 $71 $07
 +B: $13 $01 $83 $11 $FA $E4 $10 $04
 +C: $17 $C1 $24 $07 $F8 $F8 $22 $12
 +D: $61 $50 $0C $05 $C2 $F5 $20 $42
 +E: $01 $01 $55 $03 $C9 $95 $03 $02
 +F: $61 $41 $89 $03 $F1 $E4 $40 $13
 +
 +Drums
 +BD   : $01 $01 $18 $0F $DF $F8 $6A $6D
 +SD/HH: $01 $01 $00 $00 $C8 $D8 $A7 $48
 +TM/TC: $05 $01 $00 $00 $F8 $AA $59 $55
 +</code>
  
 ==== VRC7 Instrument ROM Dump ==== ==== VRC7 Instrument ROM Dump ====
 
vendor/yamaha/opl2.txt · Last modified: 2019/12/30 18:27 by lord_nightmare
 
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