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vendor:yamaha:opl2

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YM3812 or OPL2 is the “FM Operator type L (OPLII) synthesizer” used famously in the AdLib Music Synthesizer Card and Sound Blaster family of sound cards. It is a direct superset of (and shares a pin-out with) the YM3526 OPL chip, as used on the C64 FM sound expansion module. Its successor, the YMF262 or OPL3, supported 4-channel output and twice as many channels/operators and twice as many waveforms, as well as 4-op FM synthesis.

Official Documentation:

Datasheets

  • The YM3812/OPL2 datasheet can be found here.
  • The YM3526/OPL datasheet can be found here.

Known errata/omissions:

  • Omission: The /IRQ pin is open collector on both the YM3526/OPL and YM3812/OPL2.
  • Errata: The YM3526/OPL datasheet is missing the bar over the /RD and /WR signals in the truth table
  • Errata: Both the YM3526/OPL and YM3812/OPL2 datasheets list pin 1 on the diagram as VSS, it should be VCC. This is corrected in the YM3812/OPL2 application manual.
  • Errata: Bit D5(0x20) 'OPL2 MODE' of the test register(0x01) in the YM3812/OPL2 datasheet is improperly explained on both the datasheet and in the application manual, see below.

Application Manuals

  • The YM3526 application manual is not scanned. If you have a copy, please let us know!
  • The YM3812/OPL2 application manual can be found here.
  • The YMF262/OPL3 application manual can be found here.

Known errata/omissions:

  • Errata: Table 3-2 on page 12 of the YM3812/OPL2 application manual has the D4 value in the first column incorrect for the second entry from the top: the top entry is 0, and the second entry is listed as 0 but should be 1.
  • Errata: Bit D5(0x20) 'OPL2 MODE' of the test register(0x01) in the YM3812/OPL2 datasheet is improperly explained on both the datasheet and in the application manual. When bit D5 (0x20) is CLEAR, writes to registers 0xE0-0xF5 are suppressed, but the operation of said registers continues with whatever value was last written to them. This means if you set TEST(0x01) bit D5, write non-zero values to registers 0xE0-0xF5, then clear TEST(0x01) bit D5, the wave generators will continue to use the values previously written to 0xE0-0xF5 even though the chip is technically in 'non OPL2' mode. To work around this, before switching the chip to 'non OPL2' mode, ensure the chip is in 'OPL2' mode by writing 0x20 to TEST(0x01), then write values of 0x00 to all registers from 0xE0-0xF5, and finally write 0x00 to TEST(0x01).
vendor/yamaha/opl2.1552960959.txt.gz · Last modified: 2019/03/19 02:02 by cr1901