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--- azonenberg:microchip:pic32mz2048ech [2014/03/24 15:32]
azonenberg created
+++ azonenberg:microchip:pic32mz2048ech [2014/03/24 19:27]
azonenberg
@@ Line 16: / Line 16: @@
 It's //brand new//, to the point that Microchip's website still shows it as "future product" and it's not sold on anything but dev boards. We just wanted process info so the rather serious errata were a non-issue.
+Looks like a 130 nm copper process, probably 6-metal. Fill pattern looks like TSMC.
 ====== Box ======
@@ Line 41: / Line 43: @@
 ====== Die ======
-TODO
+Size is approximately 5800 x 5500 μm (31.9 mm<sup>2</sup>)
+===== Top layer =====
+Overview
+{{:azonenberg:microchip:pic32mz2048ech_bf_neo5x_4k.jpg?800|}}
+Power distribution wiring
+{{:azonenberg:microchip:pic32mz2048ech_30_bf_neo40x_annotated.jpg?600|}}
+Top left corner showing standard TSMC fill patterns
+{{:azonenberg:microchip:pic32mz2048ech_31_bf_neo20x_annotated.jpg?600|}}
+Long shot of mask rev markings
+{{:azonenberg:microchip:pic32mz2048ech_32_bf_neo20x_annotated.jpg?600|}}
+Closeup of mask rev markings. Looks like five copper layers and one thick aluminum layer.
+{{:azonenberg:microchip:pic32mz2048ech_33_bf_neo40x_annotated.jpg?600|}}
+===== Active =====
+NOR flash
+{{:azonenberg:microchip:pic32mz2048ech100_01_se_35kx_5kv_15mm.jpg?600|}}
+Litho-optimized SRAM cells
+{{:azonenberg:microchip:pic32mz2048ech100_02_se_10kx_5kv_15mm.jpg?600|}}
+{{:azonenberg:microchip:pic32mz2048ech100_03_se_45kx_5kv_15mm.jpg?600|}}
+Random gates in middle of die. Gate length looks like 130 nm.
+{{:azonenberg:microchip:pic32mz2048ech100_05_se_40kx_5kv_15mm.jpg?600|}}
+{{:azonenberg:microchip:pic32mz2048ech100_07_se_1500x_5kv_15mm.jpg?600|}}