10/100mbit SPI/parallel Ethernet controller.
44-pin QFN, decapped live.
Rough stitch of old images with Am10x objective. Need to re-shoot at higher resolution.
Map
Close-up of dense logic area at upper right:
Partial HF delayer of SRAM. Confirmed to be same process as PIC32 based on SRAM cell pitch.
mz_mit20x
