{{tag>collection_az vendor_myricom true_mask_art year_2001 type_interface type_interface/pci type_network type_network/myrinet foundry_unknown tech_unknown}}

Myricom PCI DMA ASIC from a 2gbps Myrinet NIC found by John McMaster in the MIT tech dump.

We also decapped the [[xbar|crossbar switch ASIC]] from the switch in the same cluster.

Has a Taz and a butterfly on it.

====== Board ======

From Amazon listing but the chip is labeled "PCIDMA 1.3" and looks exactly like the one we decapped.

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====== Die shots ======

Die label. Quick focus stack of two images.

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Overview. Device is a 3-metal process but has classical 2-metal design (standard cells with 7 horizontal routing tracks between them on M1, then vertical routing on M2). M3 is used for long-haul power routing and what appears to be a low-skew clock distribution grid.

Huge amounts of wasted space (multiple blank areas with no routing or logic, each several hundred microns square). The die could probably have been made quite a bit smaller if anyone bothered to try... maybe it was faster this way?

Original measurements overestimated the feature size, it now looks to be around 350nm technology.

{{:azonenberg:myricom:pcidma_03_bf_neo5x_annotated.jpg?600|}}

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Close up of random cell area.

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{{:azonenberg:myricom:pcidma_01_bf_neo40x_cropped.jpg?600|}}

Large data bus with clock grid over it (even though there's nothing for it to connect to)

{{:azonenberg:myricom:pcidma_05_bf_neo40x_annotated.jpg?600|}}

SRAM block, looks like some kind of packet buffer.

{{:azonenberg:myricom:pcidma_08_bf_neo40x_annotated.jpg?600|}}

====== Art ======

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