{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/pic/8bit year_unknown foundry_unknown tech_350nm}}

Microchip PIC12F683.

[[http://siliconpr0n.org/map/microchip/pic12f683/azonenberg_mz_am40x/|Map (am40x, some stitching artifacts)]]

====== Package ======

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====== Metal 3 ======

Size is approximately 2020 x 2240 μm (4.52 mm<sup>2</sup>) 

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===== Logo =====

{{:azonenberg:microchip:pic12f683_m3_12_bf_neo40x_annotated.jpg?300|}}

===== Mask rev marks =====

{{:azonenberg:microchip:pic12f683_m3_13_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m3_14_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m3_15_bf_neo40x_annotated.jpg?300|}}

===== EEPROM =====

{{:azonenberg:microchip:pic12f683_m3_17_bf_neo40x_annotated.jpg?300|}}

===== SRAM =====

{{:azonenberg:microchip:pic12f683_m3_16_bf_neo40x_annotated.jpg?300|}}

===== Flash =====

{{:azonenberg:microchip:pic12f683_m3_18_bf_neo40x_annotated.jpg?300|}}

===== Fuses =====

FIXME

====== Metal 2 ======

Need to take an overview pic

===== EEPROM =====

{{:azonenberg:microchip:pic12f683_m2_01_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_02_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_08_bf_neo40x_annotated.jpg?300|}}

===== SRAM =====

{{:azonenberg:microchip:pic12f683_m2_03_bf_neo40x_annotated.jpg?300|}}

===== Flash =====

{{:azonenberg:microchip:pic12f683_m2_04_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_10_bf_neo40x_annotated.jpg?300|}}

===== Fuses =====

{{:azonenberg:microchip:pic12f683_m2_05_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_09_bf_neo40x_annotated.jpg?300|}}

====== Metal 1 ======

Overetched, need to decap another chip to see

====== Poly ======

{{:azonenberg:microchip:pic12f683_poly_bf_neo10x_4k.jpg?600|}}

===== EEPROM =====

{{:azonenberg:microchip:pic12f683_poly_03_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_poly_06_bf_neo40x_annotated.jpg?300|}}

===== SRAM =====

{{:azonenberg:microchip:pic12f683_poly_01_bf_neo40x_annotated.jpg?300|}}

6T cell size is 5.25 μm x 7.35 μm (38.6 μm^2).

===== Flash =====

{{:azonenberg:microchip:pic12f683_poly_05_bf_neo40x_annotated.jpg?300|}} 

===== Fuses =====

{{:azonenberg:microchip:pic12f683_poly_04_bf_neo40x_annotated.jpg?300|}}

===== Random logic =====

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===== Random notes =====

Flash
	24 + 32 horizontal = 56 on bottom x 32 on side = 1792 unit cells
	Actual flash capacity is 2048 14-bit words = 28672 bits so each unit cell = 16 bits. 4x4?

SRAM
	4 columns of 8 bits each
	32 rows
	Horizontal WLs
	Vertical BLs
	
	5 bit row address bus
	2 bit col address bus
	
EEPROM
	256 bytes
	16 horizontal x 16 vertical = 256 unit cells
	Seems to be some dummy bits?