goodspeed:ti:tms320lc541b
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| goodspeed:ti:tms320lc541b [2022/04/26 05:23] – external edit 127.0.0.1 | goodspeed:ti:tms320lc541b [2025/08/04 21:24] (current) – external edit 127.0.0.1 | ||
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| {{tag> | {{tag> | ||
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| + | < | ||
| + | These photos are of a TMS32LC541B, | ||
| + | resold as part number AMBE2020 by DVSI. | ||
| + | |||
| + | According to the datasheet, it is mask programmed with 5K of SRAM and | ||
| + | 28K of ROM. 8K of the ROM are independently wired and can be | ||
| + | connected to either the data or the instruction bus. | ||
| + | |||
| + | Looking at the die, we might guess the following regions. | ||
| + | |||
| + | 1. A Texas Instruments logo in the center West of the chip. | ||
| + | |||
| + | 2. The 28K-word x 16-bit ROM is implemented as fourteen 2K-word banks | ||
| + | in seven pairs. | ||
| + | | ||
| + | | ||
| + | | ||
| + | | ||
| + | |||
| + | 3. Five blocks of 1K-word x 126-bit DARAM are found in the North of | ||
| + | the chip. | ||
| + | |||
| + | Page 21 of the datasheet describes a maskable option to protect the | ||
| + | contents of the on-chip memories. | ||
| + | externally originating instruction can access the on-chip memory | ||
| + | spaces. | ||
| + | |||
| + | Memory layout is on page 22. The `MP/!MC` pin flips the chip between | ||
| + | Microprocess and Microcomputer modes. | ||
| + | appears at 0x9000. | ||
| + | memory can be up to 64K of 16-bit words." | ||
| + | </ | ||
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| </ | </ | ||
| - | [[https://siliconpr0n.org/ | + | [[https://siliconprawn.org/ |
| - | * [[https://siliconpr0n.org/ | + | * [[https://siliconprawn.org/ |
| - | [[https://siliconpr0n.org/ | + | [[https://siliconprawn.org/ |
| - | * [[https://siliconpr0n.org/ | + | * [[https://siliconprawn.org/ |
goodspeed/ti/tms320lc541b.1650950587.txt.gz · Last modified: 2022/04/26 05:23 by 127.0.0.1
