Differences

This shows you the differences between two versions of the page.

--- foundry:umc [2013/12/27 23:44]
azonenberg created
+++ foundry:umc [2015/01/04 22:50] (current)
@@ Line 20: / Line 20: @@
   * 8" wafers
+===== 90 nm =====
+==== General characteristics ====
+Mostly copper with thick aluminum on the top layer.
+==== Identification ====
+==== Devices ====
+{{topic>foundry_umc +tech_90nm}}
+===== 180 nm =====
+==== General characteristics ====
+.8V core with I/O up to 3.3V. Many mixed-signal devices will have an on-die LDO for generating 1.8 from 3.3 however higher end devices such as programmable logic typically expect an external 1.8V supply.
+-5 aluminum layers with tungsten vias, titanium-based barrier metal, and cobalt silicide contacts.
+Partial design rules and FIB sections at http://siliconexposed.blogspot.com/2014/02/process-overview-umc-180nm-envm.html
+Power ring and pad layouts can vary somewhat, as does presence or absence of CMP filler between bond pads.
+On-die Flash/EEPROM option available.
+==== Identification ====
+The CMP filler pattern is distinctive and can be used as positive ID. Fill polygons are rectangles with 2:1 aspect ratio, long side oriented parallel to the prevailing routing direction.
+CMP fill pattern table (measured from XC2C32A)
+^ Layer ^ Width ^ Height ^ X pitch (μm) ^ Y pitch (μm) ^ Conditions |
+^ M4    | 3375  | 6140   | 3975         | 6975         | Overglass  |
+^ M4    | 1875  | 4875   | 3915         | 6870         | Bare metal |
+^ M3    | 3000  |  825   | 3870         | 1960         | With overglass removed, M4 present |
+^ M3    | 3075  | 1125   | 3952         | 1995         | With M3 removed |
+==== Devices ====
+{{topic>foundry_umc +tech_180nm}}
 ====== Devices ======
 {{topic>foundry_umc}}

--- sidebar [2024/04/22 04:35]
azonenberg
+++ sidebar [2024/04/22 04:36] (current)
azonenberg old revision restored (2022/05/21 00:28)
@@ Line 1: / Line 1: @@
-{{tag>collection_az year_unknown vendor_microchip vendor_micrel type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_65nm}}
+[[:start|Top level]]
-Tech node info comes from IBIS file "[Source]      Made by TSMC 65nm IBIS model file"
+Lists of devices
-http://ww1.microchip.com/downloads/en/DeviceDoc/ksz9031%20IBIS.zip
-TODO: actually decap one :){{https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.thumb.jpg}}
+    *  [[:collection|Collection]]
+      * See for copyright info
+    * [[:foundry:start|Foundry]]
+    * [[:tech:start|Process technology]]
+    * [[:type|Type]]
+    * [[:vendor:start|Vendor]]
+    * [[:year|Year]]
-[[https://siliconpr0n.org/map/micrel/ksz9031rnx/azonenberg_mz_mit20x/|mz_mit20x]]
+For newcomers
-  * [[https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.jpg|Single]] (12317x8766, 24.8946MiB)
+    * [[:navigation|Navigating the site]]
+    * [[:your_first_page|Writing your first page]]
+Other
+    * [[:conventions|Conventions]] for naming etc
+    * [[:digitized|List of digitized chips]]
+    * [[:Counterfeit]]
+    * [[:true_mask_art|True mask art]]
+    * [[:Package|Package]]
+    * [[:stdcell|Cell libaries]]
+    * [[:hdl|HDL]]
+    * [[:prog:start|Programming]]
+    * [[:TODO|TODO]]
+    * [[:Links]]