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+{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/mips year_unknown foundry_tsmc tech_180nm}}
+Microchip PIC32 microcontroller. Made on TSMC 180nm according to change notices, but measurements of channel length show closer to 250.
+  * 32 KB of SRAM
+  * 512 KB of NOR flash
+  * MIPS M4K CPU
+  * ADC
+  * PLL
+  * Other miscellaneous stuff
+IBIS model: Package made by Amkor.
+[[http://www.microchip.com/mymicrochip/NotificationDetails.aspx?pcn=CYER-29IERZ854&opennew=n|YPAA1 Rev B2 EMB Flash HE 1K Process Qualification Report]]
+Can be made at one of several fabs. One of these is TSMC Fab 11, MSL 548, EMB FLASH 1K process.
+====== Package ======
+{{:azonenberg:microchip:dscf5038_cropped.jpg?300|}}
+Markings:
+    (Microchip logo)
+    PIC32MX340F
+H-80I/MR
+    (e3)
+KGV
+====== Die ======
+Size is approximately 4280 x 4740 μm (20.29 mm<sup>2</sup>).
+Looks to be a 4-metal 250 nm process.
+===== M4 (top layer) =====
+Overview
+{{:azonenberg:microchip:pic32mx340f512h_m4_bf_neo5x-4k.jpg?1000|}}
+Interesting region in the middle of the die. Not sure what it does but provides a nice view of standard cells on lower layers.
+{{:azonenberg:microchip:pic32mx340f512h_01_bf_neo40x_annotated.jpg?600|}}
+Test points on the flash array. Probably tied to bit/word lines. Maybe used for measuring read/erase margins during characterization?
+{{:azonenberg:microchip:pic32mx340f512h_15_bf_neo40x_annotated.jpg?600|}}
+Random wiring in the middle of the die with test points
+{{:azonenberg:microchip:pic32mx340f512h_16_bf_neo40x_annotated.jpg?600|}}
+Mask rev markings
+{{:azonenberg:microchip:pic32mx340f512h_02_bf_neo20x_annotated.jpg?600|}}
+Test patterns on bottom edge
+{{:azonenberg:microchip:pic32mx340f512h_17_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic32mx340f512h_18_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic32mx340f512h_19_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic32mx340f512h_20_bf_neo40x_annotated.jpg?300|}}
+{{:azonenberg:microchip:pic32mx340f512h_21_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic32mx340f512h_22_bf_neo40x_annotated.jpg?300|}}
+===== Delayering (HF) =====
+Power busing near flash with exposed vias. ~700 nm via pitch is consistent with the 220-250 nm  process node.
+{{:azonenberg:microchip:pic32mx340f512h_23_bf_neo40x_annotated.jpg?600|}}
+===== M1 =====
+Overview
+{{:azonenberg:microchip:pic32mx340f512h_m1_bf_neo5x_4k.jpg?1000|}}
+Top left corner of SRAM array
+{{:azonenberg:microchip:pic32mx340f512h_30_bf_neo40x_annotated.jpg?600|}}
+Edge of flash array
+{{:azonenberg:microchip:pic32mx340f512h_34_bf_neo40x_annotated.jpg?600|}}
+Random standard cell region. Note large number of dummy cells. This is most likely due to their use of a cost-optimized process with less metal layers than would be necessary to route the design with more densely packed cells.
+{{:azonenberg:microchip:pic32mx340f512h_36_bf_neo40x_annotated.jpg?600|}}
+===== Active =====
+NOR flash
+{{:azonenberg:microchip:pic32mx340f512h_01_se_9000x_15kv_15mm.jpg?600|}}
+{{:azonenberg:microchip:pic32mx340f512h_02_se_35kx_15kv_15mm.jpg?600|}}
+T SRAM
+{{:azonenberg:microchip:pic32mx340f512h_04_se_4500x_15kv_15mm.jpg?600|}}
+{{:azonenberg:microchip:pic32mx340f512h_05_se_15kx_15kv_15mm.jpg?600|}}
+Random logic. 250 nm channel length.
+{{:azonenberg:microchip:pic32mx340f512h_06_se_5kx_5kv_15mm.jpg?600|}}
+{{:azonenberg:microchip:pic32mx340f512h_07_se_18kx_5kv_15mm.jpg?600|}}