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azonenberg:microchip:pic12f683 [2013/01/30 09:04] – created azonenbergazonenberg:microchip:pic12f683 [2025/10/29 19:52] (current) – external edit 127.0.0.1
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-{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/pic/8bit}}+{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/pic/8bit year_unknown foundry_unknown tech_350nm}} 
 + 
 +Microchip PIC12F683. 
 + 
 +[[http://siliconprawn.org/map/microchip/pic12f683/azonenberg_mz_am40x/|Map (am40x, some stitching artifacts)]] 
 + 
 +====== Package ====== 
 + 
 +{{:azonenberg:microchip:pic12f683_packages.jpg?600|}} 
 + 
 +====== Metal 3 ====== 
 + 
 +Size is approximately 2020 x 2240 μm (4.52 mm<sup>2</sup>)  
 + 
 +{{:azonenberg:microchip:pic12f683_m3_bf_neo10x_4k.jpg?600|}} 
 + 
 +===== Logo ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m3_12_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Mask rev marks ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m3_13_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m3_14_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m3_15_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== EEPROM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m3_17_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== SRAM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m3_16_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Flash ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m3_18_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Fuses ===== 
 + 
 +FIXME 
 + 
 +====== Metal 2 ====== 
 + 
 +Need to take an overview pic 
 + 
 +===== EEPROM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m2_01_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_02_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_08_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== SRAM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m2_03_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Flash ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m2_04_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_10_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Fuses ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_m2_05_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_m2_09_bf_neo40x_annotated.jpg?300|}} 
 + 
 +====== Metal 1 ====== 
 + 
 +Overetched, need to decap another chip to see 
 + 
 +====== Poly ====== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_bf_neo10x_4k.jpg?600|}} 
 + 
 +===== EEPROM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_03_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_poly_06_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== SRAM ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_01_bf_neo40x_annotated.jpg?300|}} 
 + 
 +6T cell size is 5.25 μm x 7.35 μm (38.6 μm^2). 
 + 
 +===== Flash ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_05_bf_neo40x_annotated.jpg?300|}}  
 + 
 +===== Fuses ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_04_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Random logic ===== 
 + 
 +{{:azonenberg:microchip:pic12f683_poly_02_bf_neo40x_annotated.jpg?300|}} 
 + 
 +===== Random notes ===== 
 + 
 +Flash 
 + 24 + 32 horizontal = 56 on bottom x 32 on side = 1792 unit cells 
 + Actual flash capacity is 2048 14-bit words = 28672 bits so each unit cell = 16 bits. 4x4? 
 + 
 +SRAM 
 + 4 columns of 8 bits each 
 + 32 rows 
 + Horizontal WLs 
 + Vertical BLs 
 +  
 + 5 bit row address bus 
 + 2 bit col address bus 
 +  
 +EEPROM 
 + 256 bytes 
 + 16 horizontal x 16 vertical = 256 unit cells 
 + Seems to be some dummy bits? 
 + 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_poly_mit100x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_poly_mit100x/|poly_mit100x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_poly_mit100x.jpg|Single]] (42213x47366, 193.979MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_poly_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_poly_mit20x/|poly_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_poly_mit20x.jpg|Single]] (8467x9392, 23.7571MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_m3_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_m3_mit20x/|m3_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_m3_mit20x.jpg|Single]] (41470x46090, 161.26MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_mz_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_mz_mit20x/|mz_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_mz_mit20x.jpg|Single]] (8484x9402, 19.1005MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_m3_mit100x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_m3_mit100x/|m3_mit100x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_m3_mit100x.jpg|Single]] (41470x46090, 161.26MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr21b_mit100x-sm/|dlyr21b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21b_mit100x-sm.jpg|Single]] (20581x22915, 83.9536MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr1_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr1_mit20x/|dlyr1_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr1_mit20x.jpg|Single]] (8444x9377, 19.2448MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr2_mit20x/|dlyr2_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2_mit20x.jpg|Single]] (8496x9402, 18.1805MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr2b_mit20x/|dlyr2b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2b_mit20x.jpg|Single]] (8446x9380, 19.6404MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr3_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr3_mit20x/|dlyr3_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr3_mit20x.jpg|Single]] (8498x9391, 13.8304MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr4_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr4_mit20x/|dlyr4_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr4_mit20x.jpg|Single]] (8514x9394, 20.0887MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr4b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr4b_mit20x/|dlyr4b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr4b_mit20x.jpg|Single]] (8471x9398, 20.0528MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr5_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr5_mit20x/|dlyr5_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr5_mit20x.jpg|Single]] (8438x9367, 20.4734MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr6_mit20x/|dlyr6_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6_mit20x.jpg|Single]] (8456x9369, 18.7448MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr6b_mit20x/|dlyr6b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6b_mit20x.jpg|Single]] (8445x9372, 18.7762MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr5b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr5b_mit20x/|dlyr5b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr5b_mit20x.jpg|Single]] (8449x9358, 21.2638MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr7_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr7_mit20x/|dlyr7_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr7_mit20x.jpg|Single]] (8449x9374, 17.7144MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr8_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr8_mit20x/|dlyr8_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr8_mit20x.jpg|Single]] (8448x9389, 19.6858MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr8b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr8b_mit20x/|dlyr8b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr8b_mit20x.jpg|Single]] (8482x9383, 17.5957MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr9_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr9_mit20x/|dlyr9_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr9_mit20x.jpg|Single]] (8456x9372, 19.2063MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr12_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr12_mit20x/|dlyr12_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr12_mit20x.jpg|Single]] (8448x9366, 20.9548MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr10_mit20x/|dlyr10_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10_mit20x.jpg|Single]] (8439x9349, 19.8967MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr14b_mit20x/|dlyr14b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14b_mit20x.jpg|Single]] (8431x9353, 21.7471MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr17b_mit20x/|dlyr17b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17b_mit20x.jpg|Single]] (8436x9358, 21.4953MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr14_mit20x/|dlyr14_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14_mit20x.jpg|Single]] (8436x9294, 17.2959MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr15b_mit20x/|dlyr15b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15b_mit20x.jpg|Single]] (8431x9352, 19.359MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr13_mit20x/|dlyr13_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13_mit20x.jpg|Single]] (8432x9367, 21.3489MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr11_mit20x/|dlyr11_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11_mit20x.jpg|Single]] (8443x9359, 18.3703MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr17_mit20x/|dlyr17_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17_mit20x.jpg|Single]] (8392x9256, 20.4785MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr13b_mit20x/|dlyr13b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13b_mit20x.jpg|Single]] (8452x9360, 22.3729MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr11b_mit20x/|dlyr11b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11b_mit20x.jpg|Single]] (8441x9374, 20.6583MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr15_mit20x/|dlyr15_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15_mit20x.jpg|Single]] (8375x9363, 22.0158MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr10b_mit20x/|dlyr10b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10b_mit20x.jpg|Single]] (8431x9354, 18.1941MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr16_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr16_mit20x/|dlyr16_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr16_mit20x.jpg|Single]] (8431x9346, 16.9531MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr27b_mit20x/|dlyr27b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit20x.jpg|Single]] (8447x9369, 19.3794MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr21_mit20x/|dlyr21_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21_mit20x.jpg|Single]] (8435x9367, 24.1969MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr19b_mit20x/|dlyr19b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19b_mit20x.jpg|Single]] (8437x9353, 24.0258MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr27_mit20x/|dlyr27_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27_mit20x.jpg|Single]] (8438x9365, 20.8986MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr18_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr18_mit20x/|dlyr18_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr18_mit20x.jpg|Single]] (8445x9359, 19.8005MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21b_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr21b_mit20x/|dlyr21b_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21b_mit20x.jpg|Single]] (8220x9147, 22.8286MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr26_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr26_mit20x/|dlyr26_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr26_mit20x.jpg|Single]] (8419x9382, 22.1698MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit20x-stack.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr27b_mit20x-stack/|dlyr27b_mit20x-stack]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit20x-stack.jpg|Single]] (8448x9379, 21.6499MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr24_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr24_mit20x/|dlyr24_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr24_mit20x.jpg|Single]] (8451x9368, 21.2026MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr20_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr20_mit20x/|dlyr20_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr20_mit20x.jpg|Single]] (8422x9348, 25.9611MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr19_mit20x/|dlyr19_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19_mit20x.jpg|Single]] (8431x9362, 24.149MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr25_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr25_mit20x/|dlyr25_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr25_mit20x.jpg|Single]] (8470x9343, 21.3888MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr23_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr23_mit20x/|dlyr23_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr23_mit20x.jpg|Single]] (8443x9367, 20.5037MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr22_mit20x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr22_mit20x/|dlyr22_mit20x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr22_mit20x.jpg|Single]] (8441x9359, 20.2048MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr14b_mit100x-sm/|dlyr14b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr14b_mit100x-sm.jpg|Single]] (20730x23088, 59.4545MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr15_mit100x-sm/|dlyr15_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr15_mit100x-sm.jpg|Single]] (20728x23032, 61.4373MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr13b_mit100x-sm/|dlyr13b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr13b_mit100x-sm.jpg|Single]] (20728x23034, 57.2009MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr2b_mit100x-sm/|dlyr2b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr2b_mit100x-sm.jpg|Single]] (20685x23213, 53.2153MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr6b_mit100x-sm/|dlyr6b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr6b_mit100x-sm.jpg|Single]] (20682x23033, 60.5888MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10b_mit100x.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr10b_mit100x/|dlyr10b_mit100x]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr10b_mit100x.jpg|Single]] (41433x46046, 141.525MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr11b_mit100x-sm/|dlyr11b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr11b_mit100x-sm.jpg|Single]] (20715x23060, 60.0917MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr18_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr18_mit100x-sm/|dlyr18_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr18_mit100x-sm.jpg|Single]] (20660x23025, 67.0523MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr19_mit100x-sm/|dlyr19_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19_mit100x-sm.jpg|Single]] (20620x22910, 67.7456MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr17b_mit100x-sm/|dlyr17b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr17b_mit100x-sm.jpg|Single]] (20724x23064, 66.2451MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr16_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr16_mit100x-sm/|dlyr16_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr16_mit100x-sm.jpg|Single]] (20694x23020, 52.2623MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr20_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr20_mit100x-sm/|dlyr20_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr20_mit100x-sm.jpg|Single]] (20644x22942, 80.113MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr19b_mit100x-sm/|dlyr19b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr19b_mit100x-sm.jpg|Single]] (20657x23007, 76.0253MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr21_mit100x-sm/|dlyr21_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr21_mit100x-sm.jpg|Single]] (20610x22935, 81.3114MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr26_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr26_mit100x-sm/|dlyr26_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr26_mit100x-sm.jpg|Single]] (20564x22896, 65.0868MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr22_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr22_mit100x-sm/|dlyr22_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr22_mit100x-sm.jpg|Single]] (20592x22918, 78.6396MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr25_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr25_mit100x-sm/|dlyr25_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr25_mit100x-sm.jpg|Single]] (20538x22885, 70.6192MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr27b_mit100x-sm/|dlyr27b_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27b_mit100x-sm.jpg|Single]] (20558x22884, 52.1351MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr27_mit100x-sm/|dlyr27_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr27_mit100x-sm.jpg|Single]] (20575x22891, 61.8223MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr24_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr24_mit100x-sm/|dlyr24_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr24_mit100x-sm.jpg|Single]] (20563x22951, 74.3218MiB) 
 + 
 + 
 +{{https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr23_mit100x-sm.thumb.jpg}} 
 + 
 +[[https://siliconprawn.org/map/microchip/pic12f683/azonenberg_dlyr23_mit100x-sm/|dlyr23_mit100x-sm]] 
 + 
 +  * [[https://siliconprawn.org/map/microchip/pic12f683/single/microchip_pic12f683_azonenberg_dlyr23_mit100x-sm.jpg|Single]] (20636x22935, 69.0032MiB)
  
-{{:azonenberg:microchip:pic12f683-m3-400x-2k.jpg?600|}} 
azonenberg/microchip/pic12f683.1359536686.txt.gz · Last modified: 2013/01/30 09:04 by azonenberg