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--- vendor:fujitsu [2017/12/09 20:01]
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+++ vendor:fujitsu [2018/01/01 06:23]
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 ====== Processes ======
-[[https://www.mentor.com/products/fpga/synthesis/partners/asic/fujitsu|Big list]]
+^ Branded vendor  ^ Branded ID  ^ Process  ^ Die ID             ^ Package  ^ Reference                                                                         ^
+| Sega            | 315-5672    | CG24     | 2H24 CG24143-4121  |          | [[http://caps0ff.blogspot.com/2017/12/sega-315-5xxx-ulas-214-217-218.html|Link]]  |
+| Sega            | 315-5673    | CG24     | 2H26 CG24243-4153  |          | [[http://caps0ff.blogspot.com/2017/12/sega-315-5xxx-ulas-214-217-218.html|Link]]  |
+| Sega            | 315-5674    | CG24     | 2H22 CG24692-4146  |          | [[http://caps0ff.blogspot.com/2017/12/sega-315-5xxx-ulas-214-217-218.html|Link]]  |
+| SNK             | LSPC2-A2    |          | 2C54 CG10103-112   |          | [[mcmaster:snk:lspc2-a2|Link]]                                                    |
+| Capcom          | DL-1727     |          | 2H22 CG24692-4122  |          | Wiki                                                                              |
+| Capcom          | DL-1525     |          | 2H22 CG24692-4123  |          | Wiki                                                                              |
+| Capcom          | DL-2027     |          | 2H20 CG24512-4105  |          | Wiki                                                                              |
+Refs:
+  * [[https://www.mentor.com/products/fpga/synthesis/partners/asic/fujitsu|Big list]]
+  * Chip IDs on this wiki
+  * http://caps0ff.blogspot.com/2017/12/sega-315-5xxx-ulas-214-217-218.html
+=== CG24 / CG25 gate arrays ===
 [[https://www.keysight.com/en/pd-B4129AJ%3Aepsg%3Apro-pn-B4129AJ/tsutsuji-fujitsu-cg24-cell-library?pm=PL&nid=-536900196.536902682&cc=CA&lc=fre|B4129AJ Tsutsuji Fujitsu CG24 Cell Library]]
-Patent EP 0136880 A1 might be of interest
+Patent US4661815 describes the architecture and customization method for those chips. They're made of predefined i/o structures framing multiple columns of double CMOS transistor pairs called "Basic cells" (BC), spaced by empty columns for routing.
+Customization is done by connecting the transistors with metal to form standard logic cells, which are then connected together and to the i/o structures.
+  * Red: input to cell.
+  * Green: output from cell.
+All pictures are from [[c0:sega:315-5674]].
+== Input pin ==
+Trace connects right behind the bonding pad.
+{{:vendor:fujitsu:fujitsu_cg24_input.jpg?400|}}
+== Output pin ==
+Trace connects to both N and P power transistors.
+{{:vendor:fujitsu:fujitsu_cg24_output.jpg?400|}}
+== Bidirectional pin ==
+One trace for input, and two individual traces for the N and P power transistors to allow tri-stating.
+{{:vendor:fujitsu:fujitsu_cg24_bidir.jpg?400|}}
+== Output driver ==
+Just a power inverter. Uses 3 BCs.
+{{:vendor:fujitsu:fujitsu_cg24_output_driver.jpg?400|}}
+== Bidirectional pin driver ==
+Top input is output level, bottom input is enable. Outputs go to the pin structure transistors.
+Described page 10 of the MBCG25512 datasheet. Uses 5 BCs.
+{{:vendor:fujitsu:fujitsu_cg24_bidir_driver.jpg?400|}}
+== Inverter with 0.5 drive strength ==
+Uses 0.5 BC.
+{{:vendor:fujitsu:fujitsu_cg24_inv_half.jpg?256|}}
+== Inverter with 1 drive strength ==
+Uses 1 BC.
+{{:vendor:fujitsu:fujitsu_cg24_inv_full.jpg?256|}}
+== 2NAND ==
+Uses 1 BC.
+{{:vendor:fujitsu:fujitsu_cg24_2nand.jpg?300|}}