Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
resistor [2012/07/01 18:07]
mcmaster
resistor [2013/10/20 10:59] (current)
Line 1: Line 1:
 ====== Depletion load ====== ====== Depletion load ======
  
-These are arranged ​with the transistor tied to be always on.  A MOSFET is classified into 3 areas of operation:​ +FIXME: compare ​with analysis at [NMOS logic design], tried to do for enhancement mode and so analysis didn't work out
-  * NMOS +
-    * Cutoff (VGS < Vth): little conduction +
-    * Triode (VGS > Vth and VDS < (VGS - Vth)): resistive +
-    * Saturation (VGS > Vth and VDS > (VGS - Vth)): conductive +
-  * PMOS +
-    * Cutoff (VGS > Vth): little conduction +
-    * Triode (VGS < Vth and VDS > (VGS - Vth)): resistive +
-    * Saturation (VGS < Vth and VDS < (VGS - Vth)): conductive+
  
-In essence a MOSFET is off if you don't apply any voltage between gate and source.  Its fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load).  ​And then there are the cases in between ​which is what we want.+Most MOSFETs encountered are enhancement.  ​In essence a its off if you don't apply any voltage between gate and source ​and fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load).  ​However, ​there are also depletion mode transistor ​which have essentially the opposite behavior: they are normally on with VGS = 0.
  
-Pulldown ​PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://​www.4004.com):​+Depletion load PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://​www.4004.com):​
  
 {{:​flylogic:​intel_400:​pullup_metal_flylogic.png}} {{:​flylogic:​intel_400:​pullup_metal_flylogic.png}}
Line 25: Line 17:
 {{:​mcmaster:​resistor:​pmos_pulldown_sch.png}} {{:​mcmaster:​resistor:​pmos_pulldown_sch.png}}
  
-(FIXME: compare with analysis at [NMOS logic design] The metal is VDD (-10V). ​For PMOS, cutoff occurs when VGS > Vth and assume Vth = -3V or something like that.  If VGS is 0 the resistor does nothing as there is no potential difference. ​ Now note that since VG = VD and so VGS = VDS.  ​We are in the triode region if VDS > VGS - Vth and so if 0 > 0 - -3V or 0 > 3V)+So the natural question to ask is how do you tell a depletion from an enhancement load MOSFET?  ​For a non-obfuscated digital design typically only depletion mode transistors have this configuration ​and are enhancement otherwise.  ​Like this, once you get into analog all bets are off and you need to be careful.
  
  
 
resistor.txt · Last modified: 2013/10/20 10:59 (external edit)
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki